JPS5918678A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET of high performance by superposing partial (111) B surface on the surface of a substrate and an epitaxial layer as the shape in which other crystalline surface exists adjacently, and selectively forming a thin operation layer on the (111) surface. CONSTITUTION:A semi-insulating GaAs substrate 11 in which a main surface 11a exists in (100) plane, is anisotropically etched, selected in approx. 2mum of width and approx. 1mum of depth, and a groove 12 of sectional trapezoid in which the bottom width is approx. 3mum and the side surface exists in (111) plane is formed. When the buffer layer 13 of semi-insulating GaAs is epitaxially formed by thermal decomposition of mixture gas of SiH4 and (CH3)3Gs, the growing speed of the (111) B surface is slow, and the oblique surface 13A of (111) B surface is accordingly presented at the certain time point. When N type impurity gas is fed from this time and epitaxial formation is continued to form an operation layer 14, the parts 14A, 14B are formed in thickness of relationship of tA>>tB by similar growing speed difference. A Pt gate electrode 15 is attached to the part 14B, and ohmic electrodes 16, 17 are attached as source and drain to the parts 14A of both sides. Since the channel length can be sufficiently short and the resistance between the source and the drain is formed to be small, high frequency characteristics can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to the semiconductor device 1, for example, a Schottky barrier gate type field effect transistor using a Qa-As l-V foreign compound semiconductor, or a similar PN junction gate type field effect transistor. This makes it possible to reliably obtain this type of semiconductor device having excellent characteristics.

Conventional compound semiconductor field effect transistor (FE)
For example, as shown in FIG. 1, a similar Qa-As compound semiconductor layer (2) of N type is formed as an active layer on a substrate (1) cut out in the (100) crystal plane of Qa-As, for example. K is epitaxially grown on this active layer (2) as
For example, for this active layer (2), the Schottky barrier (3
), a gate electrode (4) made of a metal such as platinum PT is deposited, and a source electrode (5) and a drain electrode (6) are ohmically deposited on both sides of the gate electrode (4). Become.

In the case of such a structure, its high frequency characteristics are mainly determined by the gate capacitance and the resistance between the source and the gate.
In order to reduce these, the width of the gate electrode (4) is made as narrow as possible, and the width of the source and drain electrodes (5) and (6) is made as narrow as possible.
Microfabrication is required, such as making the spacing between the two parts as small as possible. However, in this case, there is a limit to the processing accuracy and it is difficult to obtain sufficiently excellent high frequency characteristics. Various methods have also been used to reduce the resistance between the source and the gate.1 For example, as shown in FIG. A structure is adopted in which the thickness is reduced using an etching jig, and the other portions that will become the source and drain regions are made thicker to reduce the spreading resistance here. Alternatively, as shown in FIG. 3, a method is known in which the source and drain regions are doped with impurities at a high concentration by ion implantation or the like to form, for example, N-type high concentration regions.

However, in either case, the manufacturing method is complicated, and in the case of the structure shown in FIG. The disadvantage is that it is difficult to obtain an FET with good reproducibility. Further, in the case of the structure shown in FIG. 3, for example, a selective ion implantation process is required, which significantly reduces the workability.

In the present invention, these drawbacks can be solved, and an F with stable and excellent high frequency characteristics can be obtained using a simple method.
The present invention provides a method for manufacturing a semiconductor device that can produce a semiconductor device such as an ET.

That is, in the present invention, a pyrolytic vapor phase growth method for compound semiconductors, specifically K MOCVD (Metal Qrgani
In the case of the Chemical Vhpor Deposuction method, a target semiconductor device is obtained by utilizing a peculiar phenomenon of crystal growth on a substrate having an uneven structure.

That is, in the MOCVD method, the uneven structure formed on the compound semiconductor substrate is not destroyed, and the exposed structure (111)
The growth rate of the semiconductor layer on the B crystal plane is slower than that on other planes, at a rate of several tenths or less.
11) When the B plane is exposed on the surface adjacent to other crystal planes (111) In the case of only the B crystal plane, a polycrystalline semiconductor layer grows on it, but this (111)
When the B crystal plane is exposed in a narrow range and other crystal planes exist in the vicinity, (11
1) A single crystal is also grown and deposited on the B-plane, and the (111
) Utilizes the phenomenon that a single crystal growth layer on the B-plane, that is, an epitaxial growth layer forms a mirror surface.

An example in which the present invention is applied to obtaining a Schottky barrier gate type FET made of a compound semiconductor such as Ga--As will be explained with reference to FIG.

In this case, a single-crystal compound semiconductor substrate αυ of Qa-As or the like having high specific resistance, that is, semi-insulating, is provided. This substrate αD has its -main surface (lla) cut out to be a (100) crystal plane. Then, a groove a3 is formed facing the main surface (IIA) of this substrate -συ. For this groove a3, a photoresist such as AZ-1350 (trade name), which serves as an etching resist, is applied, and exposed and developed to form a window with the required width. An etching solution having anisotropy in etching with respect to the substrate αυ, for example, H3PO4:H2O2:H2O in a ratio of 1:1.
Etching is performed using a solution of 0:10. In this case, when the width of the groove α on the surface (1ta) side of the substrate αυ is selected to be 2 μm, and the depth is selected to be approximately 1 μm,
(111)A crystal planes are formed on both sides thereof, and a groove having a trapezoidal cross section with a bottom width of 3 μm is formed.

Next, a compound semiconductor, for example Q
High resistivity of a-A6 1 For example, a semi-insulating compound semiconductor layer made of a semi-insulating compound semiconductor layer α-layer is deposited by MOCVD method, that is, thermal decomposition with a mixed gas of arsine and trimethyl gallium, and then continuously. An active layer α of a 3a-As compound semiconductor is grown by a similar MOCVD method while supplying an N-type impurity gas.

The formation of the active layer α is carried out by MOCVD when growing the buffer layer a3 on the substrate αυ including the inside of the groove az as described above. After the point where the (111) B plane is generated, N-type impurities are added to the supplied gas and the growth is switched to the N-type active layer α4. That is, a buffer layer is formed in the groove aa. MOCVD K
Therefore, when performing epitaxial growth (111)
Since the growth rate of the B-plane is slower than that of the other layers, the buffer layer α3)K grown in the groove a4 will at some point become (1n)B.
A slope (13a) of the surface is generated.

Then, after the occurrence of the slope formed by the (111)B crystal plane, the active layer α is formed by supplying KN type impurity gas and subsequently performing epitaxial growth as described above. In this case, in the operating layer a4,
A buffer layer (13) is formed on the main surface (lla) having the (100) plane of the substrate aυ and on the bottom surface (12a) having the (Zoo) crystal plane in the groove Q, with the husband # (100) crystal plane The flat part (14A) kt where Uke was inherited and grown as
(111) As the B-plane, the growth rate is faster than that of the portion (14B) grown through the buffer layer (13), so the thicknesses tA and tB of the portions (14A) and (14B) are
teeth.

tA>tn.

In the present invention, a gate electrode made of a metal such as Pt that can form a Schottky barrier with respect to the compound semiconductor such as Qa-AsK is deposited on this small-thickness portion (14B), and this is used as a gate portion. , sandwiching this and using the thicker parts (14A) on both sides as the source and drain regions, respectively, ohmically deposit a drain electrode Q6) and a source cap 0η to form the intended Schottky gate FET. Obtainable.

In this example, the semiconductor device obtained by the method of the present invention is of the Qa-As Schottky barrier gate type.
According to T, since the portions that become the source and drain are formed by the thick active layer (14A), the spreading resistance can be made sufficiently small. For example, if the thickness of the large thick portion (14A) forming the source and drain of this active layer I is, for example, 1 μm, (1t
t) In the part (14B) formed as the B-plane, the thickness can be kept to about several hundred times, and the gate length corresponding to the width of the slope can also be kept to 1 μm or less, so the channel length can be reduced. It is also possible to reduce the amount of noise, and it is possible to easily obtain an FET with good high frequency characteristics.

When using the manufacturing method of the present invention, a groove a4 is formed in the substrate aυ, which is shown by the broken line with the symbol (5) in FIG. 5 so that the (111) B crystal plane exists in advance. 5. Although it is possible to form a groove shape in which the (111) B plane exists in advance, even when forming a groove shape in which the (11148 plane does not exist), when epitaxially growing the α-level buffer layer, , as mentioned above, the slope (13a) consisting of the (111)B crystal plane is naturally generated.Therefore, if the active layer a4 is then formed and its thickness is controlled, the part (14A) can be formed with high precision. (14B) thickness can be set, and the desired FBT having uniform and excellent characteristics with good reproducibility can be obtained.

Incidentally, in the above example, the part forming the gate part is formed as a slope;
As shown in the figure, a K, Qa-As compound semiconductor substrate aυ is cut out on the (111)B plane, that is, its main surface is (
A substrate having a (111) B crystal plane is formed on the main surface of the portion corresponding to the source and drain, and a few micrometers are formed on both sides of the substrate so that the width W of the portion having the (111) B main surface is, for example, about 1 μm. Etch grooves and I with a width and a depth of about 1 μm.

The main surface (lla) facing the (111) B crystal plane is left between the grooves 08 and 09, and then the active layer α4 made of, for example, an N-type compound semiconductor is formed by MOCVD similar to that described above.
It can also be formed by law. In this case as well, since the epitaxial growth rate here is fast because grooves 081 and α value face surfaces other than the (1111B crystal plane), grooves t18 and (1
Although a thick active layer portion (14A) is formed so as to bury the active layer 1, a thin epitaxial layer portion (14A) is formed in the portion facing the (111)B crystal plane of the main surface (lla) between them.
4B) occurs. Therefore, a gate electrode forming a Schottky barrier is deposited on this portion (14B) in the same manner as described above, and source electrodes aη and tte are ohmically deposited on portions (14A) above grooves II and 0, respectively. Similarly, a large part of the thickness of the working layer α fathom (14A
), and therefore the distance between the source and the drain, is, for example, 1 μm, and it is possible to obtain an FET with a small spreading resistance in the source and drain regions, that is, a small resistance between the source and the drain. As shown in FIG. 5, mesa etching is performed to etch both sides of one portion (14A), and the source and drain/electrode ←η and αe are each ohmically deposited over the circumferential surface of the mesa. You can also do that.

As described above, in the manufacturing method of the present invention, before the epitaxial growth of the active layer, a (111) B crystal plane exists in a part of the active layer, and other crystal planes exist adjacent to this. Thereafter, an active layer α4 was formed on these crystal planes.

(111) The active layer is thin in the part grown as the B crystal plane and thick in the other parts.By doing this, the channel length can be made sufficiently small as mentioned above, and the source and FET with good high frequency characteristics that reduces drain-to-drain resistance
can be obtained.

In the above example, the present invention is applied to a Schottky barrier gate type FET, but in various semiconductor devices including FETs having a gate formed by a PN junction, the active layer has excellent crystallinity and is thick. It will be obvious that the present invention can be applied to obtain a similar effect when obtaining various semiconductor devices that are desired to have both a large portion and a small portion.

[Brief explanation of drawings]

11 to 3 are cross-sectional views of conventional field effect transistors, and FIGS. 4 to 6 are cross-sectional views of field effect transistors obtained by the manufacturing method of the present invention. (11) is a compound semiconductor substrate, α fathom is an active layer, (14A
) is the large thickness part, (14B) is the small thickness part, 09 is the gate electrode, αe and α force are the drain and source electrodes. 511Figure 2Figure 3

Claims (1)

[Scope of Claims] A step of causing a (111)B crystal plane and another crystal plane to appear adjacent to each other on the surface of a compound semiconductor substrate. Thereafter, there is a step of performing pyrolytic vapor phase growth of a compound semiconductor on the surface of the compound semiconductor substrate (111) to form a relatively thin growth layer on the crystal plane B since the crystal growth rate on the crystal plane is relatively low. Manufacturing method for semiconductor devices.