JPS59184551A - Insulation type semiconductor device - Google Patents
Insulation type semiconductor deviceInfo
- Publication number
- JPS59184551A JPS59184551A JP58057873A JP5787383A JPS59184551A JP S59184551 A JPS59184551 A JP S59184551A JP 58057873 A JP58057873 A JP 58057873A JP 5787383 A JP5787383 A JP 5787383A JP S59184551 A JPS59184551 A JP S59184551A
- Authority
- JP
- Japan
- Prior art keywords
- sintered body
- semiconductor element
- semiconductor device
- substrate
- flat plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は絶縁型半導体装置に係シ、特に絶縁性基体上に
半導体素子を搭載してなる絶縁型半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an insulated semiconductor device, and particularly to an insulated semiconductor device in which a semiconductor element is mounted on an insulating substrate.
従来のこの種の絶縁型半導体装置は、半導体素子を絶縁
性の支持基板に接続して構成されているのが一般的であ
る。このように構成された半導体装置は、半導体素子と
支持基板の熱膨張係数の相違から、半導体素子と支持基
板との間の接続部に、これを運転している期間中におい
て著しい熱的交番応力を受けていることが知られている
。このため、前記支持基板は、半導体素子の熱膨張係数
にできるだけ近い材料を用いる必要があった。そこで、
シリコンに熱膨張係数が近く、かつアルミニウムに匹敵
する熱伝導率をもち、さらに絶縁性がある材料としてシ
リコンカーバイド焼結体（ヒタセラム８Ｃ）？開発され
た。このシリコンカーバイド焼結体からなる平板に半導
体素子を搭載することにより、放熱性が艮＜、シかも高
信頼度の絶縁型半導体装置を得ている。Conventional insulated semiconductor devices of this type are generally constructed by connecting a semiconductor element to an insulating support substrate. Due to the difference in thermal expansion coefficients between the semiconductor element and the support substrate, a semiconductor device configured in this manner is subject to significant thermal alternating stress at the connection between the semiconductor element and the support substrate during operation. is known to have received. For this reason, the support substrate needs to be made of a material that has a coefficient of thermal expansion as close as possible to that of the semiconductor element. Therefore,
Silicon carbide sintered body (Hitaceram 8C) is a material that has a coefficient of thermal expansion close to that of silicon, a thermal conductivity comparable to that of aluminum, and is also insulating. It has been developed. By mounting a semiconductor element on a flat plate made of this silicon carbide sintered body, an insulated semiconductor device with excellent heat dissipation and high reliability is obtained.
この場合、シリコンカーバイド焼結体平板上には、半導
体素子の電極として金属層を設けることが必要である。In this case, it is necessary to provide a metal layer on the silicon carbide sintered flat plate as an electrode of the semiconductor element.
そのために、シリコンカーバイド焼結体平板上に、金・
銀等の貴金属粉を主成分とするペーストやタングステン
等の卑金属を主成分とするペーストを印刷し、１０００
１：’以上の温度で加熱処理して金属導電層を設ける方
法が提案されている。また、シリコンカーバイド焼結体
に銅−マンガン系合金の薄膜をあらかじめ蒸着やスパッ
タ法で形成しておき、この上に銅板を重ね、加熱しなが
ら加圧接着する方法も提案されている。For this purpose, gold and
Printing a paste whose main component is noble metal powder such as silver or a paste whose main component is base metal such as tungsten, 1000
A method has been proposed in which a metal conductive layer is provided by heat treatment at a temperature of 1:' or higher. Another method has also been proposed in which a thin film of a copper-manganese alloy is previously formed on a silicon carbide sintered body by vapor deposition or sputtering, a copper plate is stacked on top of the thin film, and the film is bonded under pressure while heating.
しかしながら、これらの方法を使用できるのは、半導体
装置としての絶縁耐圧がシリコンカーバイド焼結体の電
気絶縁性で保証される場合である。However, these methods can be used only when the dielectric strength of the semiconductor device is guaranteed by the electrical insulation properties of the silicon carbide sintered body.
ところで、上記半導体装置に用いられる高熱伝導・絶縁
性シリコンカーバイド焼結体は、ベリリウム酸化物等ベ
リリウムを少量含む焼結体である。By the way, the highly thermally conductive and insulating silicon carbide sintered body used in the semiconductor device is a sintered body containing a small amount of beryllium such as beryllium oxide.
しかして、このシリコンカーバイド焼結体の電気的絶縁
性は、焼結体を構成する微結晶の結晶粒界の電気的障壁
によっているとされている。このため、前記シリコンカ
ーバイド焼結体は、その焼結体に高電圧が印加されると
電流が流れる性質をもっている。したがって、ダイオー
ド、トランジスタ、サイリスタ等高い絶縁耐圧が要求さ
れるパワー半導体素子を、従来の搭載方法でシリコンカ
ーバイド焼結体に搭載しても、上述の電流が流れる性質
によって半導体装置は熱暴走する等の問題があった。な
お、熱暴走する機構は、シリコンカーバイド焼結体にも
れ電流が流れると、半導体装置の温度が上昇することに
なり、これによってさらにもれ電流が増加するといった
繰シ返しによるものである。The electrical insulation properties of this silicon carbide sintered body are said to be due to the electrical barriers of the grain boundaries of the microcrystals that constitute the sintered body. Therefore, the silicon carbide sintered body has the property that current flows when a high voltage is applied to the sintered body. Therefore, even if power semiconductor devices such as diodes, transistors, and thyristors that require high dielectric strength are mounted on silicon carbide sintered bodies using conventional mounting methods, the semiconductor devices may suffer from thermal runaway due to the above-mentioned current flow properties. There was a problem. The mechanism of thermal runaway is that when a leakage current flows through the silicon carbide sintered body, the temperature of the semiconductor device rises, which further increases the leakage current.
本発明は上記問題点に鑑みてなされたものであり、その
目的は絶縁耐圧を尚くすると共に、放熱性がよく耐熱疲
労強度の高い絶縁型半導体装置を提供することにある。The present invention has been made in view of the above-mentioned problems, and its object is to provide an insulated semiconductor device that has a lower dielectric strength, good heat dissipation, and high thermal fatigue strength.
上記目的を達成するため、本発明は、低膨張。 In order to achieve the above object, the present invention provides low expansion.
高熱伝導、絶縁性のシリコンカーバイド焼結体の平板に
電気絶縁性の接着剤をもって、半導体素子を搭載する金
属板を接着することを％徴とする。It is characterized by bonding a metal plate on which a semiconductor element is mounted to a flat plate of highly thermally conductive and insulating silicon carbide sintered body using an electrically insulating adhesive.
以下、本発明の好適な実施例を図面に基づいて説明する
。Hereinafter, preferred embodiments of the present invention will be described based on the drawings.
第１図乃至第３図は本発明の第１実施例を説明するため
に示す図である。1 to 3 are diagrams shown for explaining a first embodiment of the present invention.
ここに、第１図は本発明に係る絶縁型半導体装置の構成
要素の放熱基板を示す断面図である。Here, FIG. 1 is a cross-sectional view showing a heat dissipation substrate that is a component of an insulated semiconductor device according to the present invention.
第１図において、放熱基板１００は、次のように製造す
る。まず酸化べＩＪ ＩＪウムを約２％含むシリコンカ
ーバイド焼結体の（厚さ３〔細〕の）平板１０３に、東
亜合成化学（株）のアロンセラミックＤの如き絶縁性の
接着剤を塗布し、次に、塗布した接着剤の上に、例えば
厚さ０．５ ［ｔｔａｎ 〕で２０［ｗ＋２１の銅板等
の金属板１０２を重ね、さらにそれらを加圧した状態で
１６時間放置した。In FIG. 1, a heat dissipation board 100 is manufactured as follows. First, an insulating adhesive such as Aron Ceramic D manufactured by Toagosei Kagaku Co., Ltd. is applied to a flat plate 103 (thickness 3 [thin]) of silicon carbide sintered body containing approximately 2% aluminum oxide. Next, on top of the applied adhesive, a metal plate 102 such as a copper plate of 20 [W+21] with a thickness of 0.5 [ttan] was placed, for example, and the plates were left under pressure for 16 hours.
その後、上記放熱基板１００を恒温槽中に入れて、１５
０Ｃで１時間加熱した。このようにして一体にされた後
の放熱基板１００を切断して断面を調べた結果、接着層
１０１の厚さは約３０〔μｍ〕に形成されていた。After that, the heat dissipation board 100 is placed in a constant temperature oven for 15 minutes.
Heated at 0C for 1 hour. As a result of cutting the heat dissipating substrate 100 integrated in this manner and examining the cross section, it was found that the thickness of the adhesive layer 101 was approximately 30 [μm].
第２図は上述のようにして構成したシリコンカーバイド
放熱基板に半導体素子を搭載した構造を示す断面図であ
る。第２図において、シリコンカーバイド放熱板１００
に８〔諺２〕のＧＴＯチップ等の半導体素子２０２を半
田箔等のろう材２０３を用りて氷菓雰囲気炉、３６０Ｃ
で接着した。ここで、半導体素子２０２としてのＧＴＯ
チップの７／−）”而１ｊ：、クロム（Ｃｒ）−ニッケ
”［Ｎ１）−銀（Ａｇ ）の蒸着面である。また、ろう
材２０３としての半田箔は、鉛（Ｐｂ）−５％、錫（Ｓ
ｎ）−１，５％、銀（Ａｇ）、含む組成のものを用いた
。FIG. 2 is a sectional view showing a structure in which a semiconductor element is mounted on a silicon carbide heat dissipation substrate constructed as described above. In FIG. 2, a silicon carbide heat sink 100
8 [Proverb 2] A semiconductor element 202 such as a GTO chip is heated in a frozen confection atmosphere furnace at 360C using a brazing material 203 such as solder foil.
I glued it with Here, GTO as the semiconductor element 202
This is the surface on which chromium (Cr)-nickel (N1)-silver (Ag) is deposited. In addition, the solder foil as the brazing material 203 is made of lead (Pb) -5%, tin (S
n)-1.5%, silver (Ag) was used.
また、上記金属板１０２は、ここでは電極板２０１が相
当することになる。なお、半導体素子２０２を搭載した
ときは、放熱基板１ｏｏは半導体支持基板２００とも称
することにする。Further, the metal plate 102 corresponds to the electrode plate 201 here. Note that when the semiconductor element 202 is mounted, the heat dissipation substrate 1oo is also referred to as the semiconductor support substrate 200.
第３図は、本発明に係る絶縁型半導体装置の実施例の基
本構成を示すものであり、第２図に示す放熱基板上に半
導体素子を搭載したものに電極を固定した構造を示す断
面図である。FIG. 3 shows the basic configuration of an embodiment of an insulated semiconductor device according to the present invention, and is a cross-sectional view showing a structure in which electrodes are fixed to a semiconductor element mounted on a heat dissipation substrate shown in FIG. It is.
第３図において、放熱基板１ｏｏの金属板２０１に半導
体素子２０２をろう材２０３で貼着した金属板（電極板
）２０１上に半導体素子２０２から、一定距離だけ離れ
た位置にＬ字型の電極端子３０２がろう材３０４をもっ
て接着されている。また、シリコンカーバイド焼結体１
０３上に前記金属板２０１から所定距離だけ離れた位置
に２つのＬ字型の電極端子３０２が、前記アロンセラミ
ックＤを用いて接着されている。前記半導体素子２０２
面上のゲートおよびカソードのコンタクト電極は、前記
のＬ字型の電極端子３０２とアルミニウム線等の電極フ
レーム３０３でそれぞれボンディングして電気的に接続
されている。In FIG. 3, on a metal plate (electrode plate) 201 in which a semiconductor element 202 is attached to a metal plate 201 of a heat dissipation board 1oo with a brazing material 203, an L-shaped electrode is placed at a certain distance from the semiconductor element 202. A terminal 302 is bonded with a brazing material 304. In addition, silicon carbide sintered body 1
Two L-shaped electrode terminals 302 are bonded onto 03 at a predetermined distance from the metal plate 201 using the aron ceramic D. The semiconductor element 202
The gate and cathode contact electrodes on the surface are electrically connected to the L-shaped electrode terminal 302 by bonding with an electrode frame 303 such as an aluminum wire.
上述のように構成された半導体装置の熱抵抗を測定した
結果、その熱抵抗は、０．３５［ｔＴ／Ｗ）であった。As a result of measuring the thermal resistance of the semiconductor device configured as described above, the thermal resistance was 0.35 [tT/W].
しかして、ＧＴＯチップに電流１０［Ａ）を通電し、シ
リコンカーバイド焼結体１０３の下面の温度が通電時に
ｌｏｏ［ｒ）、オフ時に５０〔Ｃ〕となる条件でパワー
サイクル試験した結果、２０．０００サイクルにおいて
も異常は生ぜず、特に熱抵抗の変化は認められなかった
。As a result of a power cycle test, a current of 10 [A] was applied to the GTO chip, and the temperature of the bottom surface of the silicon carbide sintered body 103 was loo [r] when the current was applied, and 50 [C] when it was off. No abnormality occurred even after 0.000 cycles, and no change in thermal resistance was particularly observed.
次に本発明の第２実施例を説明する。第２実施例は、第
１図乃至第３図に示す第１実施例とほぼ同様の構造を有
しておシ、その異なるところは、酸化ベリリウムを含む
シリコンカーバイド焼結体の３簡厚の平板１０３に、ニ
ッケルメッキしたＬ字型の銅電極端子（ゲート電極端子
とカソード電極端子）３０２．３０２および同じくアノ
ード電極端子を兼ねたＬ字型の銅板２０１を接着させる
ための接着剤に、アルミナの微結晶をフィシとして入れ
たシリコーン系接着剤を用いた点にある。Next, a second embodiment of the present invention will be described. The second embodiment has almost the same structure as the first embodiment shown in FIGS. Alumina was used as an adhesive for bonding the nickel-plated L-shaped copper electrode terminals (gate electrode terminal and cathode electrode terminal) 302, 302 and the L-shaped copper plate 201, which also served as the anode electrode terminal, to the flat plate 103. The point is that a silicone adhesive containing microcrystals is used.
すなわち、電極端子３０１および３０２を前記平板１０
３に前記接着剤で固定し、１５０Ｃで５時間加熱硬化さ
せた点が異なるのみで、他の構成には相違がない。That is, the electrode terminals 301 and 302 are connected to the flat plate 10.
The only difference is that it was fixed to No. 3 with the adhesive and heat-cured at 150C for 5 hours, but there are no other differences in the other configurations.
しかして、アノード電極板２０１上に、半導体素子（Ｇ
ＴＯチップ）２０２を半田シートを介して積層し、水素
雰囲気炉中２３０Ｃで加熱処理して接着する。半田は、
Ｐｂ−４０％、５ｎ−６０％からなる組成を有している
。前記第１実施例と同じ＜ＧＴＯチップ２０２のゲート
およびカソードのコンタクト電極と、電極端子３０２と
をアルミニウム線３０３でボンディングして、電気的に
接続してなるものである。上記した第２実施例の半導体
装置の熱抵抗を測定した結果、その熱抵抗は、ｏ、４２
［ｔ／Ｗ）であった。また、上記半導体素子を、−５５
０で１０分間、室温で５分、１５０Ｃで１０分、さらに
室温で５分を１サイクルとする温度サイクル試験を２０
０回繰シ返したが、全く異常は認められなかった。Thus, the semiconductor element (G
TO chips) 202 are stacked with a solder sheet interposed therebetween and bonded by heat treatment at 230C in a hydrogen atmosphere furnace. Handa is
It has a composition of Pb-40% and 5n-60%. Same as the first embodiment, the gate and cathode contact electrodes of the GTO chip 202 and the electrode terminals 302 are electrically connected by bonding with an aluminum wire 303. As a result of measuring the thermal resistance of the semiconductor device of the second embodiment described above, the thermal resistance was o, 42
[t/W). Further, the above semiconductor element is -55
A temperature cycle test was conducted for 20 minutes, with one cycle consisting of 0 for 10 minutes, room temperature for 5 minutes, 150C for 10 minutes, and room temperature for 5 minutes.
The test was repeated 0 times, but no abnormality was observed.
第４図乃至第６図は本発明の第３実施例を示すものであ
る。4 to 6 show a third embodiment of the present invention.
第４図は本発明の第３実施例を示す平面図である。第５
図は第４図のＡ−Ａ線に沿う断面図である。さらに、第
６図は同第３実施例を示す斜視図である。FIG. 4 is a plan view showing a third embodiment of the present invention. Fifth
The figure is a sectional view taken along line A-A in FIG. 4. Furthermore, FIG. 6 is a perspective view showing the third embodiment.
これらの図において、２％の酸化ベリリウムを含むシリ
コンカーバイド焼結体［：３７Ｘ６２Ｘ３闘〕の平板１
０３に、アルミナを含む無機質接着剤Ｃ東亜合成化学（
株）のアロンセラミックＷ）１０１を塗布し、次いで、
その上に、厚さ０．５〔簡〕の銅の電極端子４０３およ
び４０４を固定し、室温で２４時間放置後、１５０ｔ：
’で１時間加熱して硬化せしめた。このシリコンカーバ
イド放熱板１００上にダイオード４０１を６箇と、これ
らダイオード４０１の一方の電極および電極４０３とを
接続する電極フレーム４０２とを、Ｐｂ−５（９）
％、８ｎ−１，５、Ａｇからなる半田シート２０３を介
在させて、３６０Ｃの水素雰囲炉で加熱処理し、３相ダ
イオードブリツジの回路構成の半導体装置を形成した。In these figures, a flat plate 1 of silicon carbide sintered body [:37X62X3] containing 2% beryllium oxide is shown.
03, an inorganic adhesive containing alumina C Toagosei Chemical (
Co., Ltd.'s Aron Ceramic W) 101 was applied, and then
Copper electrode terminals 403 and 404 with a thickness of 0.5 [simple] were fixed thereon, and after being left at room temperature for 24 hours, 150 tons:
' to harden it by heating for 1 hour. Six diodes 401 are placed on this silicon carbide heat sink 100, and an electrode frame 402 connecting one electrode of these diodes 401 and the electrode 403 is made of Pb-5(9)%, 8n-1,5, Ag A solder sheet 203 consisting of the above was interposed, and heat treatment was performed in a hydrogen atmosphere furnace at 360 C to form a semiconductor device having a three-phase diode bridge circuit configuration.
第６図は、この３相ダイオ一ドブリツジ半導体装置に、
ポリエチレンを主成分とする樹脂ケースをシリコン系接
着剤（東芝シリコーン（株）のＴ８Ｅ３２２）で接着し
、減圧下で脱泡後１５０Ｃで２時間加熱硬化させた。樹
脂ケースの上部の孔５０２から、日立化成（株）の２液
性エポキシ樹脂（ＫＥ ５２３−１６ ＰＲ−５）を流
し込んだ後、１２０Ｃで２時間、さらに１５０ｃで７時
間加熱して硬化させた。Figure 6 shows this three-phase diode bridge semiconductor device.
A resin case containing polyethylene as a main component was adhered with a silicone adhesive (T8E322 manufactured by Toshiba Silicone Corporation), and after degassing under reduced pressure, it was heated and cured at 150C for 2 hours. After pouring a two-component epoxy resin (KE 523-16 PR-5) from Hitachi Chemical Co., Ltd. into the hole 502 at the top of the resin case, it was heated at 120C for 2 hours and then at 150C for 7 hours to harden it. .
このように構成された３相ダイオ一ドブリツジ半導体装
置の熱抵抗を測定した結果、この熱抵抗は、ダイオード
１箇当たり０．２０ Ｃｃ／Ｗ）であった。さらに、第
１実施例と同じく（−５５Ｃ４＋室温＋ｘｓｏＣ）とい
う温度サイクルの条件で３００サイクルの温度サイクル
試験をしたが、異常は認められなかった。As a result of measuring the thermal resistance of the three-phase diode bridge semiconductor device configured as described above, the thermal resistance was 0.20 Cc/W per diode. Furthermore, a temperature cycle test was conducted for 300 cycles under the same temperature cycle conditions as in the first example (-55C4+room temperature+xsoC), but no abnormality was observed.
（１０）
第７図は本発明の実施例を複合半導体装置に応用した場
合を示す斜視図である。第７図において、符号６００は
ＧＴＯモジュール、６０１はＧＴＯチップ、６０２はク
リ−ホイールダイオード、６０３はアルミニュウム線、
６０４はダイオード電極フレーム、６０５は電極端子、
６０６は樹脂ケース、６０７は樹脂である。(10) FIG. 7 is a perspective view showing a case where the embodiment of the present invention is applied to a composite semiconductor device. In FIG. 7, reference numeral 600 is a GTO module, 601 is a GTO chip, 602 is a Cree-wheel diode, 603 is an aluminum wire,
604 is a diode electrode frame, 605 is an electrode terminal,
606 is a resin case, and 607 is resin.
本発明の各実施例は、このような複合半導体装置にも応
用することができる。Each embodiment of the present invention can also be applied to such a composite semiconductor device.
本実施例によれば、シリコンカーバイド焼結体に電気絶
縁性の接着剤で金属板を接着したシリコンカーバイド放
熱板を作成したので、これによシ、シリコンカーバイド
放熱板の絶縁性は、シリコンカーバイド焼結体と絶縁性
の接着層で分担でき、パワー半導体素子の搭載に必要な
数ＫＶの耐圧を得ることができる。According to this example, a silicon carbide heat sink was created by bonding a metal plate to a silicon carbide sintered body with an electrically insulating adhesive. The sintered body and the insulating adhesive layer can share the burden, and it is possible to obtain a withstand voltage of several KV necessary for mounting a power semiconductor element.
本実施例によれば、半導体素子から外部への電気の取シ
出しのため電極端子を設けるに当たシ、電極端子をシリ
コンカーバイド焼結体に直接、上記の接着剤で取シ付け
ることができるため、半導（１１）
体装置の製造が容易となる。According to this embodiment, when providing an electrode terminal for extracting electricity from a semiconductor element to the outside, it is possible to attach the electrode terminal directly to the silicon carbide sintered body using the above adhesive. This facilitates the manufacture of semiconductor (11) devices.
本実施例によれば、シリコンカーバイド焼結体の熱伝導
率が艮いため、熱抵抗の小さい半導体装置を得ることが
できる。According to this embodiment, since the thermal conductivity of the silicon carbide sintered body is high, a semiconductor device with low thermal resistance can be obtained.
本実施例によれば、半導体装置の中に配置した半導体素
子の電気的絶縁をとること、および外部の湿気等、半導
体素子の電気特性の阻害要因となる雰囲気からの保護の
ために樹脂を被覆、モールドする場合において、半導体
素子を搭載したシリコンカーバイド放熱板の熱膨張が小
さく熱歪が小さいため、被覆、モールドする樹脂層を薄
くできる。また、これによシ、半導体装置を小型化でき
るとともに、二次的にモールドした樹脂側からの放熱性
が良くなるという効果もある。According to this embodiment, the resin is coated to electrically insulate the semiconductor element placed in the semiconductor device and to protect it from external moisture and other atmospheres that may inhibit the electrical characteristics of the semiconductor element. In the case of molding, the silicon carbide heat sink on which the semiconductor element is mounted has low thermal expansion and low thermal distortion, so the resin layer for covering and molding can be made thin. Moreover, this also has the effect that the semiconductor device can be made smaller and that heat dissipation from the secondary molded resin side is improved.
次に、本発明の変形例について説明する。本発明は上述
した実施例のほか、種々の態様にて実施することができ
る。Next, a modification of the present invention will be described. The present invention can be implemented in various embodiments in addition to the embodiments described above.
まず、接着剤としては、有機系の接着剤、例えばエポキ
シ系の一液型あるいは二液型の接着剤、エポキシイミド
系接着剤やイミド系、アミド系等（１２）
の接着剤をはじめシリコン系接着剤音用いることができ
る。この場合注意する必要があるのは、以上の有機系接
着剤は、材料によっては耐熱性が低いのもあシ、シリコ
ンカーバイド焼結体に半田等のろう材で接着する際に、
熱劣化するものもある点である。また、有機系接着層は
、熱伝導率が悪いのもあシ、半導体装置の熱抵抗が太き
くなシ易いので、選択の際に、この点を考慮し、耐熱性
に優れ、伝導率の良好なものを選定する必要がある。First, adhesives include organic adhesives, such as epoxy one-component or two-component adhesives, epoxyimide adhesives, imide adhesives, amide adhesives, etc. (12), and silicone adhesives. Glue sound can be used. In this case, it is important to note that the above organic adhesives may have low heat resistance depending on the material, and when bonding to the silicon carbide sintered body with a brazing material such as solder,
The point is that some materials deteriorate due to heat. In addition, organic adhesive layers have poor thermal conductivity and tend to increase the thermal resistance of semiconductor devices, so take this into account when selecting organic adhesive layers, which have excellent heat resistance and low conductivity. It is necessary to select a good one.
次に、接着剤としては、無機系の接着剤、例えば東亜合
成化学の「アロンセラミック」等、無機質ポリマーと耐
火性セラミックを主成分とするものを用いることができ
る。この場合、主成分の耐火性セラミックは、ジルコニ
アやシリカ、およびアルミナが用いられるが、アルミナ
を主成分とすれば熱伝導率が太きいために良好である。Next, as the adhesive, an inorganic adhesive, such as "Aron Ceramic" manufactured by Toagosei Chemical Co., Ltd., whose main components are an inorganic polymer and a refractory ceramic can be used. In this case, the refractory ceramic used as the main component is zirconia, silica, or alumina, but if alumina is used as the main component, it is good because of its high thermal conductivity.
一方、シリコンカーバイド焼結体の平板に接着する金属
板としては、銅、銅合金、アルミニウムおよび銅とイン
バーのクラツド板等を用いることができる。On the other hand, as the metal plate to be bonded to the flat plate of the silicon carbide sintered body, copper, copper alloy, aluminum, a clad plate of copper and invar, etc. can be used.
（１３）
〔発明の効果〕
以上述べた・ように本発明によれば、シリコン、カーバ
イド焼結体の平板に金属板を電気絶縁性の接着剤をもっ
て貼着したので、絶縁耐圧を高くすると共に、放熱性が
良く、かつ耐熱疲労強度の高い絶縁型半導体装置を提供
することができる効果がある。(13) [Effects of the Invention] As described above, according to the present invention, a metal plate is attached to a flat plate of silicon or carbide sintered body using an electrically insulating adhesive, so that the dielectric strength voltage is increased and This has the effect of providing an insulated semiconductor device with good heat dissipation and high thermal fatigue strength.
また、本発明によれば、シリコンカーバイド焼結体に金
属板を直接貼着できるので、半導体装置を容易に提供で
きる効果がある。Further, according to the present invention, since the metal plate can be directly attached to the silicon carbide sintered body, it is possible to easily provide a semiconductor device.
第１図は本発明の第１実施例における放熱基板を示す断
面図、第２図は同第１実施例における半導体支持基板を
示す断面図、第３図は同第１実施例の半導体装置を示す
断面図、第４図は本発明の第３実施例を示す平面図、第
５図は第４図のＡ −Ａ線に沿う断面図、第６図は同第
３実施例を示す斜視図、第７図は本発明の実施例を複合
半導体装置に応用した例を示す斜視図である。
１００・・・放熱基板、１０１・・・接着層、１０２・
・・金（１４）
属板、１０３・・・シリコンカーバイド基板の平板、２
００・・・半導体支持基＆、２０１・・・電極板、２ｏ
３・・・ろう材、２０２・・・半導体素子、３０１，３
０２゜（１５）
第 １ 図
％ｚ 図
第３図
第４図FIG. 1 is a sectional view showing a heat dissipation substrate in a first embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor support substrate in the first embodiment, and FIG. 3 is a sectional view showing a semiconductor device in the first embodiment. 4 is a plan view showing a third embodiment of the present invention, FIG. 5 is a sectional view taken along line A-A in FIG. 4, and FIG. 6 is a perspective view showing the third embodiment. , FIG. 7 is a perspective view showing an example in which the embodiment of the present invention is applied to a composite semiconductor device. 100... Heat dissipation board, 101... Adhesive layer, 102...
...Gold (14) metal plate, 103...Flat plate of silicon carbide substrate, 2
00... Semiconductor support base &, 201... Electrode plate, 2o
3... Brazing metal, 202... Semiconductor element, 301,3
02゜(15) Figure 1 %z Figure 3 Figure 4
Claims (1)
導体装置において、前記絶縁性基体をシリコンカーバイ
ドの焼結体からなる平板とし、該平板に金属板を電気絶
縁性の接着剤をもって貼着して放熱基体を構成し、前記
放熱基体の金属板に前記半導体素子をろう材をもって接
着してなることを特徴とする絶縁型半導体装置。1. In an insulated semiconductor device in which a semiconductor element is mounted on an insulating substrate, the insulating substrate is a flat plate made of a sintered body of silicon carbide, and a metal plate is attached to the flat plate with an electrically insulating adhesive. 1. An insulated semiconductor device characterized in that the semiconductor element is bonded to a metal plate of the heat dissipation base using a brazing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58057873A JPS59184551A (en) | 1983-04-04 | 1983-04-04 | Insulation type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58057873A JPS59184551A (en) | 1983-04-04 | 1983-04-04 | Insulation type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59184551A true JPS59184551A (en) | 1984-10-19 |
Family
ID=13068098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58057873A Pending JPS59184551A (en) | 1983-04-04 | 1983-04-04 | Insulation type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59184551A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0666601A2 (en) * | 1994-02-04 | 1995-08-09 | ABB Management AG | Turn-off semiconductor device |
| US6521992B2 (en) * | 2000-04-21 | 2003-02-18 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Semiconductor apparatus |
-
1983
- 1983-04-04 JP JP58057873A patent/JPS59184551A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0666601A2 (en) * | 1994-02-04 | 1995-08-09 | ABB Management AG | Turn-off semiconductor device |
| EP0666601A3 (en) * | 1994-02-04 | 1998-04-29 | Asea Brown Boveri Ag | Turn-off semiconductor device |
| US6521992B2 (en) * | 2000-04-21 | 2003-02-18 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Semiconductor apparatus |
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