JPS5918451U - フオトダイオ−ドの構造 - Google Patents

フオトダイオ−ドの構造

Info

Publication number
JPS5918451U
JPS5918451U JP11379782U JP11379782U JPS5918451U JP S5918451 U JPS5918451 U JP S5918451U JP 11379782 U JP11379782 U JP 11379782U JP 11379782 U JP11379782 U JP 11379782U JP S5918451 U JPS5918451 U JP S5918451U
Authority
JP
Japan
Prior art keywords
substrate
photodiode
photodiode chip
electrode terminal
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11379782U
Other languages
English (en)
Inventor
北浦　眞潮
徳洋 井上
Original Assignee
ミノルタ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ミノルタ株式会社 filed Critical ミノルタ株式会社
Priority to JP11379782U priority Critical patent/JPS5918451U/ja
Publication of JPS5918451U publication Critical patent/JPS5918451U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のフォトダイオードを示す分解斜視図、第
２図はこの考案の第１実施例によるフォトダイオードの
完成品前の段階における分解斜視図、第３図は上記第１
実施例によるフォトダイオードの水平断面図、第４図は
同フォトダイオードの垂直断面図、第５図はこの考案の
第２実施例に、よるフォトダイオードの完成品前の段階
における分解斜視図、第６図は上記第２実施例によるフ
ォトダイオードの水平断面図、第７図はこの考案の第３
実施例によるフォトダイオードの水平断面図である。 １．７・・・・・・基板、７ａ・・・・・・収納部、７
ｂ・・・・・・取付段部、８，９・・・・・・電極端子
部材、１５・・・・・・フォトダイオードチップ、１６
・・・・・・フィルター、１７・・・・・・貫通孔、１
８．１９・・・・・・金線。 ２′■°　　　　　　　　　第５ 第２図 １図　　　　　　　　　１４

Claims (1)

  1. 【実用新案登録請求の範囲】 １　フォトタイオードチップと、このフォトダイオード
    チップを収納した所定形状の絶縁性プラスチック材料か
    ら成る基板と、この基板に上記フォトダイオードチップ
    の収納部を避けてインサートされ、一端がその基板の側
    面から上記収納部に収納されたフォトダイオードチップ
    の受光面と平行乃至は略平行に突出すると共に他端がそ
    の基板内において露出した導電性物質から成る一対の電
    極端子部材と、その基板内において露出した電極端子部
    材の各一端と上記フォトダイオードチップのアノード及
    びカソードを接続する金線と、上記フォトダイオードチ
    ップの受光面を覆うように上記基板に取付けられたフィ
    ルターとを備えたことを特徴とするフォトダイオードの
    構造。 ２　上記基板がその基板内において露出した上記電極端
    子部材の一端に沿う部分にその一端の幅よりも小径の貫
    通孔を有することを特徴とする実用新案登録請求の範囲
    第１項記載のフォトダイオードの構造。
JP11379782U 1982-07-26 1982-07-26 フオトダイオ−ドの構造 Pending JPS5918451U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11379782U JPS5918451U (ja) 1982-07-26 1982-07-26 フオトダイオ−ドの構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11379782U JPS5918451U (ja) 1982-07-26 1982-07-26 フオトダイオ−ドの構造

Publications (1)

Publication Number Publication Date
JPS5918451U true JPS5918451U (ja) 1984-02-04

Family

ID=30263290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11379782U Pending JPS5918451U (ja) 1982-07-26 1982-07-26 フオトダイオ−ドの構造

Country Status (1)

Country Link
JP (1) JPS5918451U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4841166B1 (ja) * 1969-08-01 1973-12-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4841166B1 (ja) * 1969-08-01 1973-12-05

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