JPS59181660A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a static type memory cell wherein the generation of parasitic MOS transistors is prevented, the surface of a double-layer wiring is flat, and the short circuit between wirings, etc. is prevented by a method wherein a load resistor is formed by oxidizing the side part of the first layer polycrystalline Si after side etching, growing the second layer polycrystalline Si. CONSTITUTION:A gate oxide film 4 is formed over the entire surface of a P type semiconductor substrate 1, successively depositing a nitride film over the entire surface, a window is opened therein, and a P type high concentration impurity is ion-implanted, next a field oxide film is formed. The first layer poly Si layer 5 to form a gate electrode and a word line is grown over the entire surface, N type diffusion is performed, and the surface of said layer 5 is oxidized, thus forming an SiO2 film 12. A resist film is formed over the entire surface and then patterned, and said layer 5 is etched. Thereafter, an oxide film 12 is formed also on the side part of said layer 5. The second layer poly Si 7 forming a high resistor is grown over the entire surface and patterned. A PSG film 8 is grown over the entire surface and selectively etched, thus forming contact holes. Then, aluminum wires 10 are formed by vapor- depositing aluminum over the entire surface and patterning it.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a static memory cell load resistor.

(2) Background of the technology A static memory cell is basically a flip-flop, and this memory cell has a resistive load as shown in the circuit diagram of Fig. 1, and a resistive memory cell as shown in the circuit diagram of Fig. 2. There is also a transistor memory cell. Note that in these figures, TI.

1゛2 N-channel MOS transistor, T3.1゛4
Example 1) Shows channel MO3l-run lister.

In the memory cell with a resistance load as shown in Figure 1, the stand-high current consumption increases or the cell can be made smaller. Although the Anasai-Fukuroki is an extremely small C-MOS, the cell is large. The memory cell shown in FIG. 1 is suitable for mass production when stand-high current consumption is not a major problem.

(3) Prior Art and Problems Although the memory cell shown in FIG. 1 has the advantage of negative II resistance, it is required to reduce the area of the cell. In addition, in high resistance negative front type memory cells, parasitic ? There is a problem in that the resistance of the 1O3 transistor is generated, and as a result, the resistance decreases, current flows in the direction shown by the arrow in the figure, and standby current consumption increases.

The high resistance load type memory cell shown in FIG. 1 is shown in FIG. 4 (bl), which is a plan view of FIG. In the figure, 1 is a P-type semiconductor substrate, 2 is a field oxide film, 3 is an N'-type scattered layer 4 is a gate oxide film of silicon dioxide (5i02), 5 is a first layer of polycrystalline silicon (polysilicon), 6 and 12 are 5i
02 is an insulating film, 7 is a second layer polysilicon (high resistance layer),
8 is phosphorus silicate glass (PSG) crotch (hoshu ta),
9 indicates a contact window, and 14 indicates a through ball. Is it due to the parasitic MO5l Funjisk mentioned above? ll flow increase is the 4th
It occurs in the direction shown by the arrow [in Fig. 4 (al).
The second layer polysilicon 7 is shown with sand on al, and 5L
, 5b4J show the T]-1 line and the νcc line formed by the first layer polysilicon, respectively.

N+ type expansion IM 3 no 1/ Hell is l-1 (higb
, about 5V), electrons are attracted to the high-resistance diffusion layer side of the 215th polysilicon 7, and the parasitic MO5+-
This creates a run-disk, lowers the resistance, and increases stand-high current consumption.

Also, as shown in FIG. 4 (C1), the first layer polysilicon 5
If the alignment between the contact hole and the second layer polysilicon 7 is misaligned, and the contact hole is misaligned, a short circuit may occur between the aluminum wiring 10, which is the hint line or the Vss line, and the first or second layer polysilicon. There are cases where M1
Although it is desired that the surface of the aluminum wiring 10 be as flat as possible, it is difficult to flatten the aluminum wiring 10 in the two-layer structure shown in the figure.

(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention prevents the formation of parasitic MO5l-run listers in static memory cells. Another object of the present invention is to provide a method for forming a static memory cell in which short circuits between any of the 2rf4 wirings and the human line or Vss line formed on the surface of the memory cell are prevented.

(5) Structure and object of the invention According to the present invention, in a method for forming a negative ij resistance of a static type memory cell, a first layer of polycrystalline silicon for a gate electrode of a transistor constituting the memory cell is formed. Then, a step 41Ij of side-etching the side facing the contact window formation region and then oxidizing the side, and growing a second layer of polycrystalline silicon forming a high resistance to form the side-etched portion. This is achieved by providing a method for manufacturing a semiconductor device characterized in that it includes a double wire embedded therein to form the load resistor.

(6) Examples of the invention Embodiments of the present invention will be explained in detail below with reference to the drawings.

The inventor of this application discovered that in current static memory cells that use polysilicon as a high-resistance material, when this polysilicon is patterned by conisoting G, unnecessary polysilicon remains around the polysilicon pattern. There is a problem in removing the 111j resistor polysilicon, but rather, we thought of actively leaving what remains like this and using it as 111j resistor polysilicon.

A method for manufacturing a static memory cell according to the present invention will now be described with reference to FIG.

Forming gate oxide 11 on the second surface of P-type semiconductor substrate 1,
Subsequently, nitride dust (not shown) is deposited on the entire surface, a window is opened in it, P-type high concentration impurities are ion-implanted, and then field oxidation is performed to form a pattern 2.

In the figure, reference numeral 11 indicates 1) +-type channel cup) layer;
9 indicates a contact hole, and 14 indicates a through hole.

In addition, it is a 1-fold view along the BB line of FIG. 5 (bl is FIG. 5 ta).

Then K+-? First layer polysilicon layer 15 (non-doped) for forming Li pole and So 1-line
is grown, N-type diffusion is performed on this polysiliman layer, and then the surface of the polysilicon layer 5 is oxidized to form a Sin: film 1.
form 2. Next, a sixth polysilicon layer is applied to the first polysilicon layer 5.
As shown in the sandy area in figure (a), it opens, i.e. 5i.
The 02 film and the first PA polysilicon 5 are etched as shown in Fig. 6 (bl).Then, the entire surface is coated with a resin film, patterned, and the photo ion is etched as shown in Fig. 6 (bi).
An N+ type scattered layer 3 is formed by ion implantation as shown by the arrow. In addition, Fig. 6 (in al., 5a
and 5b indicate the word line and Vcc line formed by the first layer polysilicon, respectively;
FIG. 1 is a sectional view taken along line 13-B of FIG. Next, the resist IIA described above is removed.

Next, a resist film is formed on the entire surface, and it is coated as shown in FIG. 7(a).
Patterning is performed as shown in FIG.

Next, the 11th polysilicon 5 is etched and etched (see the sectional view of FIG. 7 fb along the line B-13 in FIG. 7 (at O)). This etching is carried out by etching accompanied by cytoconisotching, and a portion of the eaves 2 with a mark 13 is formed on the side of the first polysilicon layer 5 facing the contact window formation portion. Subsequently, the resist film is removed, and an oxide film 12 is also formed on the sides of the first layer polysilicon 5 by oxidation. This eaves portion 13 is shown in bold lines in the 1 mm plan views from FIG.

Next, a resist film is formed on the entire surface, and it is shown in FIG.
Pattern as shown in . In the figure, the sandy area shows the area where the resist IIA has been removed. Next, 5 exposed in the part without this resist pattern
11% of iO2 is etched to form a contact window between the first layer polysilicon 5 and the second layer polysilicon ribbon to be formed in the next step and a contact window to the diffusion layer 3-, and then the resist film is removed. Figure 8 (In the sectional view of bl, the part covered by line B-13 is B-1 of No. 8I button 1(a)
This is the sandy part along line B.

Next, 2j to polysilicon 7 to form high resistance on the entire surface.
(non-doped) is grown and patterned as shown in the plan view of FIG. 9(a). In the figure, the sanded areas are areas where polysilicon remains. Next, the resist film used for etching is removed. The surface of the 21st polysilicon layer 7 is oxidized to prevent the phosphorus of the PSC film to be formed later from spreading to the second layer polysilicon layer 7.
lo: II history 6 is formed (see FIG. 9 (b), which is a cross-sectional view along line B-B of al).

FIG. 7 (as explained with reference to t+l, No. 1ri)
A canopy portion 13 was formed on the side of the polysilicon 5 facing the contact window. This eaves portion 13 is shown in Fig. fis 9 (C1 and Fig. fA9 (dl), which are cross-sectional views taken along line B-C and line D-D in Fig. 9 fal. The non-doped second layer polysilicon 7 used as a resistor is grown under reduced pressure so as to wrap around the eaves part 3 to form an ir+i resistor 7a.
Serve it to Woll. The polysilicon high I thus formed
The width of the Jk resistor 7d is as small as about 1/10 of the width of a conventional resistor.

In the two-layer structure of normal polysilicon, ζ is shown in Figure 9 (d
) The polysilicon 7a grown on the eaves of the polysilicon 7a remains in the area shown in the figure and causes a short circuit. However, according to the present invention, the side surface of the first layer polysilicon 5 is grown as shown in FIG. 7(b).
4. Since the oxide film 12 is formed as described in Section 4, there is not only no risk of short circuit, but also this polysilicon 7a is actively used as a high resistance material.

Next, 1) SG Ill 8 is grown on the entire surface, and it is selectively etched to form a contact ball 9. Aluminum is vapor-deposited on the entire surface, and it is patterned to form an aluminum line 10 (see FIG. 10).・])).

In the same figure, the aluminum wire is
and Vss line 10b, and the second layer polysilicon indicated by 7b has a high resistance and serves as a dummy for aligning the channel lengths.

Referring to the circuit diagram of FIG. 10(e), the 1157th polysilicon 5 is located at the Vss line, and the H (high) and L (l
It is understood that there is no influence of the gate of the adjacent first layer polysilicon 5. transistor is O
Even if the high voltage is applied to the gate and the high resistance drops, the high resistance is connected to the opposite side, and the parasitic transistor generates electricity. In addition, as can be understood from a comparison between FIG. 4(C) and FIG. 10tb+, which shows the 11'3 crease section at B B 1jjL in FIG. 10(a), the static type memory according to the present invention Although the cell has a 2+i polysilicon structure, the area near the contact window is flat, and the risk of short circuit between the aluminum wire and the polysilicon is extremely reduced, and the junction capacitance between the gate and the diffusion layer is also reduced.

(7) Effects of the Invention As explained in detail above, according to the present invention, a high-resistance polysilicon whose width is about 1/↓0 of a conventional resistor is at the same height as the first layer polysilicon. As a result, a transparent transistor is generated, the resistance decreases, and the stand-high current consumption increases.The load resistance is large and the area is small. The production of another ink-type memory cell becomes rJJ.

[Brief explanation of the drawing]

Figures 1 and 2 are circuit diagrams of a static type memory cell with a negative (;;J or resistor 1) [and a transistor; A circuit diagram for explaining the raw transistor, Fig. 4 (al is a conventional starai-tsuk type Nomoly cell Q), Fig. 1+i,
Figure 4 (bl is a cross-sectional view of B-13 cotton in Figure 4(a), Figure 4 (C1 is an example of misalignment of the multilayer polysilicon and the contact hole)
The top views and FIGS. 5 to 10 are diagrams of a static type memory cell in the process of carrying out the method of the present invention. 1- Silicon attack 1st attack, 2- Field 1st attack,
3.7. N+ type diffusion, 4-day 1-oxide film, 5-
1j polysilicon, 5a-word line, 5b--Vc
c line, 5 -- 5i02 month 9hi, 7
− Σi′: J 2 b: i polysilicon, 78−
High resistance, 7b-high/low 1) [dummy, 8-screaming ISG film, 9
-Contact hole, 10- Aluminum wire, 10a
Bit cotton, 10b-Jss wire, 11-P” channel cut, 12'-5i02 crotch, 13-eaves part (Q) Fig. 9 Fig. 9 (d)

Claims (1)

[Claims] In the 6 methods of forming a load resistance of a static memory cell, a first layer of polycrystalline silicon for the gate electrode of the transistor constituting the memory cell is formed, and its side facing the contact window formation region is Zaydoe, Ching;
Thereafter, the method further includes the step of oxidizing the side portion (4'iH5) and growing a second layer of polycrystalline silicon forming a sheet resistance to bury the site-etched portion and form the load resistance. Semiconductor notes 1. A method of manufacturing a ji device.