JPS59180815A - Data reading circuit - Google Patents

Abstract

PURPOSE:To deliver an accurate data pulse signal even in case a false peak of a read signal is produced by the noises, crosstalks, etc., by providing a pulse width checking circuit to a data reading circuit of a magnetic disk device to deliver only the data pulse signals that have the pulse width larger than the prescribed value. CONSTITUTION:A pulse width checking circuit 30 detects the pulse width of a data pulse signal Pi which is given from a data generating circuit 11 in accordance with the peak with which the read signal R read out of a magnetic disk is detected by a differentiating circuit 10. Then only the signals Pi having their pulse widths larger than the prescribed value are delivered as data pulse signals Po. This signal Po is applied also to a gate control signal generating circuit 14. Thus it is possible to deliver an accurate data pulse signal Po on the basis of the correct peak position of the signal R.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data succession circuit used in a Wednesday, Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, and Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, Friday, and Friday, Friday, and other devices.

[Technical background of the invention and its problems] Generally, a magnetic disk device is provided with a data read circuit that extracts read signals and recorded data successively output from a recording medium (magnetic disk). This data reading circuit is required to reliably extract data while preventing the effects of noise, crosstalk, and the like. In particular, in recent years, the recording density of data in magnetic disk devices has increased, so the possibility that erroneous data will be extracted due to the effects of noise, crosstalk, etc. has increased.

For this reason, conventionally, a data successive output circuit as shown in FIG. 1, for example, has been proposed. That is, the read signal SR read from the magnetic disk is input to the differentiating circuit IO, and this differentiating circuit 70 detects its peak. The output signal D of the differentiating circuit 10 is given to the data generating circuit 11.

On the other hand, read signal R is applied to gate control signal generation circuit l2. This gate control essence generation circuit 12 outputs a gate control signal based on a predetermined threshold value (TH, , 'I'' in FIG. 2) (2) to the delay circuit I3. The output of the differentiating circuit 10 is 1.The gate control signal is delayed by a constant 1;)1 in order to match the timing with ￥D.3:, Or is output to the data generation circuit 11.Data generation circuit It is the signal Gl
Based on the differential quantity! A signal is input from 1'81o, and the gate control signal 0 from the gate control signal generation circuit 14 is input.
2. By prohibiting the input of a signal based on 11-, a data pulse signal WP having a predetermined pulse width is outputted as shown in FIG. Here, the gate control signal generation circuit 14 outputs a gate control signal Q o 2 based on both the signal 01 and the data pulse signal P (FIG. 2).

In such a conventional data pulse circuit, both the output signal of the differentiating circuit and the gate control signal Or are
There is a possibility that 4-axis movement 7'lZW may be generated due to noise, etc. Therefore, each peak point a − of the read signal R
In order to accurately output the data pulse signal P with the dK pattern, it is necessary to adjust the timing between the gate control signal GF and the signal Q'D using the delay circuit 13. That is, the signal (
Read the timing between 11 and 0. The timing on the real ['1> of 2 R (peak point and peak point I:i
f',) 1p (Origi sale [7 signal R is 1 value T
I(,, T I(,,, (11″1 sip timing)
Therefore, for example, if an erroneous pulse occurs near the front of the peak of the read signal R due to noise etc., the data pulse P as shown in Fig. 2 will be generated. Incorrect data d' will be generated.

That is, on the data pulse P, the original peaks based on the read signal E:゛R exist at positions a, b, c, and d2, and e-ri d' indicates a peak that is equal to lj'm. It turns out.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to improve readout performance (J+, where false peaks are generated, and However, the data readout circuit h'j can output an iF-standard data pulse signal based on the original peak of Sendashi Jingin,
+1j, (to provide.

rSummary of the Invention] In the present invention, in a magnetic disk drive; in an even data reading circuit, a data pulse generation circuit outputs a data pulse signal with a predetermined pulse width based on a peak of a successive signal detected by a differentiating circuit. is configured to do so. This data pulse signal is applied to a pulse width test circuit. The pulse width inspection circuit is configured to detect the pulse width of the data pulse signal and output only those data pulse signals whose pulse width is equal to or larger than a predetermined value.

Even if an erroneous data pulse signal is generated due to a false peak in the readout signal, it is possible to remove that error and output only the data pulse signal accurately. .

[Embodiments of the invention]

Regarding one embodiment of the present invention with reference to page IZ for the following:
i+p, clarify. FIG. 3 shows data reading 11 according to the present invention.
FIG. 1 is a block diagram 1 showing an octagonal configuration of i11+.”3.

In the figure, the data generation circuit 11 is a 30-digit pulse width inspection circuit.
Detects the pulse width of the data pulse (Fj' S P 1) given from 7, and converts only the data pulse signal PI whose pulse width is equal to or greater than a preset value into the data pulse signal PO.
Output as . This data pulse signal Pa is 1. It is also provided to the gate control signal generation circuit 14. Note that the other configurations are the same as those in FIG. 1 of the manual, so the same reference numerals 7 are given and explanations are omitted.

Here, the data readout +il path in FIG. 4 is specifically constituted by a circuit as shown in FIG. 4, for example. In other words, the amount of data generated! ? 811 is Compa L/-Yu ao
The comparator 40t/C is provided with an output signal I) of the differentiating circuit IO.

The output signal '4ABhz of the comparator 40 is applied to the input terminals of each set 1 of the NAND circuits 42 and 43, respectively.

Each output signal B1B of this NAND f01K (2, (,?)
2 are applied to each input terminal of the NAND circuit h'844. The NAND circuit 44 outputs a data pulse signal, which is its output signal Pi, to the pulse width test circuit 3o. The pulse width test circuit 30 is connected to the delay line 45 and the same! t′+<46, delay line 4
5 and one of the input terminals of the ant circuit 6 have input terminals P1 and 1.5. Ru. And times #
46 receives the output signal of the delay line 45 at the other input terminal, and outputs the output signal as a data pulse 4-R-PO.

On the other hand, the gate control signal generating circuit 12 includes a comparator 47 and an inverter 48, as shown in FIG. 4, and one input terminal of the comparator 47 is given a read signal R. This comparator 47 is connected to the divided voltage applied to the other input terminal by 1. (Nijita Ei 1 value T H
,, T H,, a series of letters? A pulse synchronized with the timing when crossing the line C is output from the delay circuit 13 at the delay line 49 (49). The signal O1 is output to both the ;i','2 input terminals of the NAND circuit 11 and the inverter 50.
; Is there a gate system? ill 4(:”-'r occurrence 1
The data pulse No. 4g Po is given to the clock terminal of the flip 70 of the old l1gr4 and the pull 51 of the 5I.
Each output signal F7. Sled F2.

They are output to the third input terminals of the NAND circuits 42 and 43, respectively. The output signals Fr and F2 correspond to the signal G3 in FIG. 3 above. In addition, in the 41st unit, 528 to 52C are resistors.

The operation of this configuration will be explained. first,
Read j7 signal R% read from the magnetic disk + differential circuit IO and gate system 6! (assuming that it is given to the j signal generation circuit 12. As a result, I), a signal Pi as shown in the 51st sword is output from the data generation circuit rr. This (2 Gin Pi is (11 units), as shown in FIG. 4, is the output of the data generation amount i, !877 [Raku 44]. That is, as shown in FIG. 6, Signal Gl, N, AI
, A2. Fl.

In F2, the logical formula “(Al-N-IJ) + (A2・
When the external conditions such as Gl-F2)J hold, 41
The No. 1 PI is Jji (r'i, l). When this signal P1 is given to the pulse width inspection circuit 30, the Igo E and 1. is applied to one input terminal of the AND circuit 46.

AND times: The other inputs of 1'846; 1.1 child has
When the signal 11 i is applied to the target 1. ing. Therefore, the signal P1 and the signal P1 are logically ANDed, and the data pulse 4g, which is true in the bundle, is output as shown in FIG. That is,
Data pulse garbled on signal F1, original peak of readout IinV<, R, 45. There are only data pulses corresponding to a to d. Therefore, the pulses at the false peak positions (7θ to 72 in FIG. 6) caused by noise, crosstalk, etc. are output from the pulse 71M inspection circuit 30 and are turned off.

By the way, the data series shown in Figure 4 (Rakuhs valid JK motion 1 to 1-7, accurate data pulse 4, 4 PO
output], the following six-line property is required.

JJ, the false peak occurs before the peak position of the page2, and the false peak interval is 1) smaller than the delay time of the delay lithography 45 of the pulse width inspection circuit 90, Lj,1.
It is a meeting. Second, fake peaks are good peak locations.)
This is a case where 17 occurred before, and moreover, 31 occurs in Nil more than the delay time of delay time 45 'h''-1. , continuous noise, etc. 11 - Since it is difficult to multiply by 0 for true peaks and hills,
It's impossible to get a KO in such a short time.

In this way, the differential circuit 10 detects the peak of the read signal 1-7H continuously outputted from the magnetic disk at F+1°, and the data generating circuit II outputs the data pulse signal Pi based on the peak. In the present invention, even if a pulse corresponding to a false peak caused by noise, crosstalk, etc. is generated on the data/</response signal Pi of the data generation circuit II, the pulse width inspection circuit 30 ) That unnecessary Noculus can be removed. Therefore, the IF data pulse can be reliably outputted at the +E peak of the read signal R.

〔Effect of the invention〕

As described in detail above, according to the present invention, a false peak occurs due to noise, crosstalk, etc. in the data readout circuit of a 6-star disk device. It is possible to remove the Tajita pulse signal R. Therefore, it is possible to reliably output an accurate data pulse signal wiped at the iE L peak position of the following 1. Tomesode. In addition, it is possible to reliably read data written on a magnetic disk.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of seven conventional data readout circuits, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a block diagram of a data readout circuit according to an embodiment of the present invention. A block diagram showing the basic configuration, Figure 4 is the third
Data in the figure, a diagram showing an example of the IA interbody circuit of the extraction circuit, a timing chart for explaining the operation in Figure 3, 1st digit of sentence 51, and Figure 6 for explaining the operation in Figure 4. This is a timing chart. lO...differential quantity) Raku, 11...de - evening departure 1=
Circuit, 30...Pulse width inspection circuit.

Claims (1)

[Claims] (Reading means for extracting the sales signal 1 from the magnetic disk; a differentiation circuit for detecting the peak of the readout signal outputted from the reading means; and a differentiation circuit for detecting the peak of the readout signal based on the output signal of the differentiation circuit. data pulse generating means for outputting a data pulse signal with a predetermined pulse width according to the data pulse generation means; and detecting the pulse width of the data pulse signal outputted from the data pulse generating means and generating a data pulse whose pulse width is equal to or greater than a predetermined value. 1. A data continuous output circuit comprising: a pulse width inspection circuit that outputs only a signal.