JPS5720063A - Buffer memory control circuit of facsimile receiver - Google Patents
Buffer memory control circuit of facsimile receiverInfo
- Publication number
- JPS5720063A JPS5720063A JP9415080A JP9415080A JPS5720063A JP S5720063 A JPS5720063 A JP S5720063A JP 9415080 A JP9415080 A JP 9415080A JP 9415080 A JP9415080 A JP 9415080A JP S5720063 A JPS5720063 A JP S5720063A
- Authority
- JP
- Japan
- Prior art keywords
- buffer memory
- memory control
- shift register
- register
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/38—Circuits or arrangements for blanking or otherwise eliminating unwanted parts of pictures
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Fax Reproducing Arrangements (AREA)
Abstract
PURPOSE:To prevent an all-black picture from being recorded at the remaining part of recording paper on which necessary picture data has been recorded, by clearing the output of a shift register right after a one-frame picture is sent from the shift register. CONSTITUTION:In the latch circuit 24B of a buffer memory control part 24, the count value of the number of write lines is latched and a line-number counter 24A goes up in response to a line end signal LG generated each time a one-line read is completed. Then, the count values of counters 24A and 24B are compared with each other by a comparator 24C, which when the both coincides with each other, outputs a signal REP to stop the reading operation. Consequently, the output of a register 23 are cleared right after one-frame picture data is sent from the shift register 23, thereby forcing data in the register 23 to ''0''s.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9415080A JPS5720063A (en) | 1980-07-10 | 1980-07-10 | Buffer memory control circuit of facsimile receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9415080A JPS5720063A (en) | 1980-07-10 | 1980-07-10 | Buffer memory control circuit of facsimile receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5720063A true JPS5720063A (en) | 1982-02-02 |
Family
ID=14102347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9415080A Pending JPS5720063A (en) | 1980-07-10 | 1980-07-10 | Buffer memory control circuit of facsimile receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5720063A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58198962A (en) * | 1982-05-17 | 1983-11-19 | Fuji Xerox Co Ltd | Scanner for light beam |
JPS593625A (en) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | Empty confirmation control system of image buffer of printer |
JPS5963882A (en) * | 1982-10-05 | 1984-04-11 | Canon Inc | Picture forming device |
-
1980
- 1980-07-10 JP JP9415080A patent/JPS5720063A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58198962A (en) * | 1982-05-17 | 1983-11-19 | Fuji Xerox Co Ltd | Scanner for light beam |
JPH0158911B2 (en) * | 1982-05-17 | 1989-12-14 | Fuji Xerox Co Ltd | |
JPS593625A (en) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | Empty confirmation control system of image buffer of printer |
JPS631614B2 (en) * | 1982-06-30 | 1988-01-13 | Fujitsu Ltd | |
JPS5963882A (en) * | 1982-10-05 | 1984-04-11 | Canon Inc | Picture forming device |
JPH0530105B2 (en) * | 1982-10-05 | 1993-05-07 | Canon Kk |
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