JPS59180787A - Printer - Google Patents

Printer

Info

Publication number
JPS59180787A
JPS59180787A JP58055798A JP5579883A JPS59180787A JP S59180787 A JPS59180787 A JP S59180787A JP 58055798 A JP58055798 A JP 58055798A JP 5579883 A JP5579883 A JP 5579883A JP S59180787 A JPS59180787 A JP S59180787A
Authority
JP
Japan
Prior art keywords
data
address
buffer
memory
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58055798A
Other languages
Japanese (ja)
Other versions
JPH0156409B2 (en
Inventor
Hiroki Takashima
高嶋 裕樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58055798A priority Critical patent/JPS59180787A/en
Publication of JPS59180787A publication Critical patent/JPS59180787A/en
Publication of JPH0156409B2 publication Critical patent/JPH0156409B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)

Abstract

PURPOSE:To increase the speed of data writing with one image buffer by reading out data already written in the image buffer by a prescribed unit and writing data of the prescribed unit in the memory of the read out address. CONSTITUTION:Printing data P1-Pn are constituted of a prescribed unit (for example, one line quantity) and already written in a memory 1. When a data request signal DR is generated from a printing section 2 and also a write instruction W is generated from a processor 3, a control section 4 generates control signals B and E. The control signals B and E slowly advances an address counter 9 by actuating a read control section 5, opening an AND gate 7, and passing through a clock CL1, designate an address A1, and send data P1 to the printing section 2. After delaying by T second by means of a delay circuit 10, another address counter 12 is slowly advanced by actuating a write control section 13, opening an AND gate 11, and passing through another clock CL2, data Q1 are written in the address A1.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明はプリント用バッファを有するプリンタに関する
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a printer having a print buffer.

(b)  従来技術と問題点 レーザビームプリンタでは、プリントデータを一時蓄え
るイメージバッファを有する。プリンタの高速化を図る
一手段として、このイメージバッファを2個を設ける方
法があり、これは一方のイメージバッファ内のプリント
データをプリント中に、他方のイメージバッファに他の
装置(例えば処理装置)からのプリントデータを書込ん
で、転送時間の知縮を図るものである。周知のようにイ
メージバッファは、その容量が犬なので、これを2個設
けることは、プリンタのコストアップを招くことになる
。これに対し、イメージバッファ内に既に書込まれてい
るデータを所定単位で読出し、この読出された後に所定
単位のデータの書込みを直チに行えば、イメージバッフ
ァは1個でJ?!、しかも高速化の目的を達成すること
ができる。
(b) Prior Art and Problems Laser beam printers have an image buffer that temporarily stores print data. One way to increase the speed of a printer is to provide two image buffers.This means that while the print data in one image buffer is being printed, the print data in the other image buffer is transferred to another device (such as a processing device). This is to reduce the transfer time by writing the print data from the printer. As is well known, the capacity of the image buffer is limited, so providing two image buffers increases the cost of the printer. On the other hand, if the data already written in the image buffer is read out in a predetermined unit, and then the predetermined unit of data is written immediately after being read, the number of image buffers is J? ! , moreover, the purpose of speeding up can be achieved.

(C)  発明の目的 本発明は上記の点に着目したものであシ、プリント速度
を向上するプリンタの提供を目的とする。
(C) Object of the Invention The present invention has focused on the above points, and an object of the present invention is to provide a printer that improves printing speed.

(d)  発明の構成 本発明は、バッファと、プリント部とを有するプリンタ
において、前記バッファのアドレスを選択する第1のア
ドレス選択手段と、該第1のアドレス選択手段が選択し
たアドレスを所定時間経過後に選択する第2のアドレス
選択手段と、前記バッファに所定単位のデータを順次書
込む手段と、該バッファ内のデータを所定単位で順次読
出す手段とを備え、前記第1のアドレス選択手段によシ
バッファ内のデータを所定単位で読出したのち、前記第
2のアドレス選択手段を用い、該所定単位のデータが読
出された前記バッファのアドレスに、他の装置からのデ
ータを所定単位で書込むことを特徴とするプリンタであ
る。以上のように本発明は、1個のイメージバッファ内
のデータを所定単位で読出し、この読出しが行われた直
後に、そのアドレスに新たなデータの書込みを行うこと
によQ1プリント効率の向上全図った゛ものである○(
e)  発明の実施例 以下、本発明を図面によって説明する。図面は本発明の
一実施例を説明するブロック図である。
(d) Structure of the Invention The present invention provides a printer having a buffer and a print section, including a first address selection means for selecting an address of the buffer, and an address selected by the first address selection means for a predetermined period of time. the first address selection means, comprising: second address selection means for selecting after the elapse of time; means for sequentially writing predetermined units of data into the buffer; and means for sequentially reading data in the buffer in predetermined units; After reading the data in the transfer buffer in predetermined units, the second address selection means is used to write data from another device in predetermined units to the address of the buffer from which the predetermined unit of data was read. This is a printer that is characterized by the ability to As described above, the present invention improves Q1 printing efficiency by reading data in one image buffer in predetermined units and writing new data to that address immediately after this reading. It was planned○(
e) Examples of the invention The present invention will be explained below with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.

図面におけるプリントデータPは所定単位(例えば1ラ
イン分)のデータP、〜Pnで構成され、同様にプリン
トデータQもデータQ、〜Qnで構成されるものとする
。なお図面におけるメモリ1には、既にプリントデータ
Pが書込まれているものと4し、このメモリ1内のプリ
ントデータハj臆次(pt〜Pnの順で)読出され、プ
リント部2へ送られて、プリントが行われる。図面にお
いて、プリント部2からデータ要求信号DRが発せられ
、且つプロセサ3からも書込命令Wが発せられた場合、
これを受けた制御部4は制御信号B及びEを発する。
It is assumed that the print data P in the drawings is composed of a predetermined unit (for example, one line) of data P, -Pn, and similarly, the print data Q is also composed of data Q, -Qn. It is assumed that the print data P has already been written in the memory 1 in the drawing, and the print data in the memory 1 is read out (in the order of pt to Pn) and sent to the print section 2. and printing is performed. In the drawing, when the data request signal DR is issued from the print unit 2 and the write command W is also issued from the processor 3,
Upon receiving this, the control section 4 issues control signals B and E.

制御信号Bは読出制御部5を起動し、また制御信号Eは
ANDゲート7を開とするので、パルス発生部8からの
クロックパルスCL、によシ、アドレスカウンタ9は1
つ歩進し、メモリlのアドレスA、が選択される。従っ
てこのアドレスA、のデータP1が読出制御部5によシ
読出され、プリント部2へ送出される。一方、制御信号
Eは、遅延回路10(遅延時間:1秒)を経て、制御信
号E′3− とな!+、ANDゲート11に達する。これによシアン
ドゲート11は開となるが、その時点は、アンドゲート
7が開となった時点よりT秒遅れることになる。パルス
発生部8からのクロックパルスCL!によシアドレスカ
ウンタ12が歩進し、メモリ1のアドレスA、が選択さ
れ、このアドレスA1に制御信号E′によシ起動された
畳込制御部13によシ、プロセサ3からの書込データQ
の最初のり データQ、が新たに書込まれる。このよテ読出/書込制
御が、メモリ1のアドレスA2〜Anに対しても同様に
行われる。従って1つのメモリのデータの所定単位デー
タの読出しに1ステツプ遅れて所定単位データの書込み
がスムーズに行われることになる。
The control signal B activates the read control section 5, and the control signal E opens the AND gate 7, so that the clock pulse CL from the pulse generator 8, the address counter 9 is set to 1.
The address A of memory l is selected. Therefore, the data P1 at this address A is read out by the readout control section 5 and sent to the printing section 2. On the other hand, the control signal E passes through the delay circuit 10 (delay time: 1 second) and becomes the control signal E'3-! +, reaches AND gate 11. This opens the AND gate 11, but this time is T seconds later than the time when the AND gate 7 opens. Clock pulse CL from pulse generator 8! The address counter 12 increments, the address A of the memory 1 is selected, and the convolution control unit 13 activated by the control signal E' writes to this address A1 from the processor 3. Data Q
The first data Q, is newly written. This read/write control is similarly performed for addresses A2 to An of the memory 1. Therefore, writing of the predetermined unit data of data in one memory is smoothly performed with a one-step delay in reading the predetermined unit data.

(f)  発明の効果 以上のように本発明は1個のイメージバッファメモV+
用いるのみで、メモリ内のデータのプリント部への送出
と、該メモリ内への新たなデータの書込みとを実現する
ことによシ、データの転送時間の短縮化を図ったもので
あり、プリント効率4− を向上しうる利点を有する。
(f) Effects of the Invention As described above, the present invention provides one image buffer memo V+.
By simply using the printer, data in the memory can be sent to the print section and new data can be written into the memory, thereby reducing the data transfer time. It has the advantage of improving efficiency 4-.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を説明するブロック図であり、
図中に用いた符号は次の通りである01はメモリ、2は
プリント部、3はプロセサ、4は制御部、5は読出制御
部、6はプリント制御部、7,11はANDゲート、8
はノくルス発生部、9.12はアドレスカウンタ、10
は遅延回路、13は読出制御部、14はプリントヘッド
、A、。 A2はアドレス、B、 E、 E’は制御信号、CL、
 。 CL2.CL3はクロックパルス、DRはデータ要求信
号、P+ PIT P21 P”t Q+ Q+  は
データ、Tは時間、Wは書込指令を示す0
The drawing is a block diagram illustrating an embodiment of the present invention,
The symbols used in the figure are as follows: 01 is the memory, 2 is the print section, 3 is the processor, 4 is the control section, 5 is the readout control section, 6 is the print control section, 7 and 11 are AND gates, 8
9.12 is the address counter, 10
1 is a delay circuit, 13 is a readout control unit, and 14 is a print head. A2 is the address, B, E, E' are the control signals, CL,
. CL2. CL3 is a clock pulse, DR is a data request signal, P+ PIT P21 P”t Q+ Q+ is data, T is time, W is 0 indicating a write command

Claims (1)

【特許請求の範囲】[Claims] バッファと、プリント部とを有するプリンタにおいて、
前記バッファのアドレスを選択する第1のアドレス選択
手段と、該第1のアドレス選択手段が選択したアドレス
を所定時間経過後に選択する第2のアドレス選択手段と
、前記バッファに所定単位のデータを順次書込む手段と
、該バッファ内のデータを所定単位で順次読出す手段と
を備え、前記第1のアドレス選択手段によシバッファ内
のデータを所定単位で読出したのち、前記第2のアドレ
ス選択手段を用い、該所定単位のデータが読出された前
記バッファのアドレスに、他の装置からのデータを所定
単位で書込むことを%徽とするプリンタ。
In a printer having a buffer and a print section,
a first address selection means for selecting an address of the buffer; a second address selection means for selecting the address selected by the first address selection means after a predetermined time has elapsed; writing means; and means for sequentially reading data in the buffer in predetermined units, and after the data in the buffer is read out in predetermined units by the first address selection means, the second address selection means A printer that writes data from another device in a predetermined unit to the address of the buffer from which the predetermined unit of data was read.
JP58055798A 1983-03-31 1983-03-31 Printer Granted JPS59180787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58055798A JPS59180787A (en) 1983-03-31 1983-03-31 Printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58055798A JPS59180787A (en) 1983-03-31 1983-03-31 Printer

Publications (2)

Publication Number Publication Date
JPS59180787A true JPS59180787A (en) 1984-10-13
JPH0156409B2 JPH0156409B2 (en) 1989-11-30

Family

ID=13008928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58055798A Granted JPS59180787A (en) 1983-03-31 1983-03-31 Printer

Country Status (1)

Country Link
JP (1) JPS59180787A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284260A2 (en) * 1987-03-14 1988-09-28 Brother Kogyo Kabushiki Kaisha Raster scan type printer
JPS63317349A (en) * 1987-06-19 1988-12-26 Canon Inc Printer
JPH01297247A (en) * 1988-05-26 1989-11-30 Canon Inc Image recording apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53100735A (en) * 1977-02-15 1978-09-02 Hitachi Ltd Print control device
JPS5590176A (en) * 1978-12-28 1980-07-08 Ricoh Co Ltd Reader
JPS5822440A (en) * 1981-07-31 1983-02-09 Anritsu Corp Printer for high-speed input data

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53100735A (en) * 1977-02-15 1978-09-02 Hitachi Ltd Print control device
JPS5590176A (en) * 1978-12-28 1980-07-08 Ricoh Co Ltd Reader
JPS5822440A (en) * 1981-07-31 1983-02-09 Anritsu Corp Printer for high-speed input data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284260A2 (en) * 1987-03-14 1988-09-28 Brother Kogyo Kabushiki Kaisha Raster scan type printer
JPS63317349A (en) * 1987-06-19 1988-12-26 Canon Inc Printer
JPH01297247A (en) * 1988-05-26 1989-11-30 Canon Inc Image recording apparatus

Also Published As

Publication number Publication date
JPH0156409B2 (en) 1989-11-30

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