JPS6054050A - Information processing device - Google Patents

Abstract

PURPOSE:To store the address of error occurrence in a stack by delaying a response signal to a central processing unit at an error occurrence time and setting the central processing unit to the holding state to extend the access cycle. CONSTITUTION:When an error occurs, a response signal 11 from a storage device 2 is inputted to a delay circuit 14, and this output and the response signal 11 are inputted to a selecting circuit 15. The selecting circuit 15 selects the response signal 11 when an interrupt request signal 4 is nonactive, but the circuit 15 selects the output of the delay circuit 14 when the signal 14 is active. Consequently, if the interrupt request signal 4 in nonactive, that is, if an error does not occur, the response signal 11 is inputted to a wait control circuit as it is. If the interrupt request signal 4 is active, that is, if the error occurs, the output of the delay circuit 14 is inputted to the wait control circuit, and a holding signal is inserted to an error occurrence cycle, and an interrupt request signal 6 is accepted in the error occurrence cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an error interrupt processing circuit that occurs during data input/output.

As shown in FIG. 2, a conventional information processing device has a central processing unit 1, a storage device 2, and an interrupt control circuit 3, and receives an interrupt generated when accessing the storage device 2 as an input/output signal. Request signal (IRQ) 4 and external interrupt request signal (I
RI, IR2, ■1 also 3) 5, the interrupt request signal (INT) 6 of the interrupt control circuit 3 to the central processing unit 1, the start-up signal (MEMR) 7 to the storage device 2, and the Write signal (MEMW) 8 and storage device 2
A bus (DB) 9 for reading and writing data transfer, a basic clock (CLK) 10 for the central processing unit 1, a response signal (ACK) 11 indicating completion of access to the central processing unit 1 of the storage device 2, etc. .

FIG. 2 is a waveform diagram showing a timing chart when data is output from the storage device 2 of FIG. 1.

The period Tl-T4 represents one access cycle of the central processing unit l. Period T2. When a read command (read signal 7) is sent to the storage device u2 between T3, the storage device 2
places the read data on the transfer path 9 and sends an access end signal (response signal 11) to the central processing unit 1.

When the central processing unit l receives the response signal 11, it deactivates the WAIT control circuit and enters the next access cycle. For example, a parity check is performed on the read data on the transfer path 9, and if an error occurs, an interrupt request signal 4 to the interrupt control circuit 3 is generated. In this interrupt control circuit 3, since arbitration with other interrupt request signals 5 is normally performed, a certain amount of time is required. After arbitration, the interrupt control circuit 3 outputs an interrupt request signal 6 to the central processing unit l, or the central processing unit l has already entered the next access cycle. Since the interrupt request signal 6 is normally accepted at the end of the access cycle, in conventional devices, as shown in FIG. 2, error processing cannot be performed immediately after the cycle in which the error occurs; Processing will be performed after l access cycles. If, for example, a jump instruction is entered between these access cycles, there is a drawback that the address where the error has occurred cannot be searched.

An object of the present invention is to provide an information processing device that improves these drawbacks.

The present invention provides an information processing device comprising a central processing unit and a storage device, wherein the storage device has a storage data path, and generates an interrupt request signal to the central processing unit during an access period of the central processing unit. An information processing device characterized by having a control circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing an information processing apparatus according to an embodiment of the present invention. In the same figure, this information processing device is equipped, and the input/output signals include an interrupt request signal (IRQ) 4 generated when accessing the storage device M2, and an external interrupt request signal (IRQ) 4.
IR1, IR2, IR3) 5, an interrupt request signal (INT) 6 for the central processing unit 1 of the interrupt control circuit 3, a read signal (MEMR) 7 for the memory device [2, and a memory device @
2, the read and write data transfer bus (1)B) 9 for the storage device 2, the basic clock (CLK) lO of the central processing unit, and the central processing unit before adding the delay. Response signal (ACK) to l
11, and a response signal (DACK) 12 indicating completion of access to the central processing unit 1 after adding a delay. now,
The response signal 11 returned from the storage device 2 when an error occurs is input to the delay circuit 14, and the output of this delay circuit 14 and the response signal 11 are input to the selection circuit 15. The selection circuit 15 selects the response signal 1 when the interrupt request signal 4 is inactive.
'l is selected, and the output of the delay circuit 14 is selected when it is active. Therefore, when the interrupt request signal 4 is inactive, that is, when no error has occurred, the response signal 11 is input as is to the wait (WAIT) control circuit, and as shown in the timing chart of FIG. It behaves similarly. Furthermore, when the interrupt request signal 4 is active, that is, when an error occurs, the output of the delay circuit 14 is input to the WAIT control circuit, and as shown in FIG. The input request signal 6 can be accepted between cycles in which an error occurs.

As described above, according to the present invention, when an error occurs, a delay is added to the response signal 11 to the central processing unit IK, the central processing unit I is placed in the WAIT state, and the access cycle is extended, so that the interrupt request signal 6 Since the error occurrence address can be generated between generation cycles and stored in the stack, it is possible to operate in the same way as conventional devices when no error occurs, and therefore it can operate without losing access speed. By delaying the response signal to the central processing unit when an error occurs, it is possible to accept an interrupt request between the cycles in which the error occurs, and to enter the error processing route immediately after the cycle in which the error occurs, thereby ensuring that the error address is secured. Effects such as being able to do this can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional information processing device, and FIG. 2 is a waveform diagram showing a timing chart of the conventional information processing device.
FIG. 3 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 4 is a waveform diagram showing a timing chart of the information processing apparatus according to an embodiment of the present invention. In the top view, l... Central processing unit, 2...
...Storage device, 3...Interrupt control circuit, 4...
...Interrupt request signal, 14...Delay circuit, 1
5...Selection circuit, 2...Interrupt request input signal, 6...Interrupt request output signal, 7...
Bladder ejection signal, 8...Writing signal, 9...
・Data transfer bus, lO...Basic clock input, 11...Response signal, 12...Response signal, 16...Way 1-(WAIT) Control circuit input terminal, 13...Delay circuit input terminal, 17
...Delay circuit output terminal, WAIT...
Weight control circuit output signal T, to T4...
Access cycle period, TW...wait period. Agent: Susumu Uchihara, patent attorney 1, l+, -,,.

Claims (1)

[Claims] In an information processing device that includes a central processing unit and a storage device, the storage device has an interrupt signal generation circuit that generates an interrupt signal when an error occurs during input/output of stored data, and transmits an interrupt request signal to the central processing unit to the central processing unit. An information processing device comprising a control circuit that generates a signal during an access period of the processing device.