JPS59180463U - Ceramic multilayer wiring board - Google Patents

Ceramic multilayer wiring board

Info

Publication number
JPS59180463U
JPS59180463U JP7414083U JP7414083U JPS59180463U JP S59180463 U JPS59180463 U JP S59180463U JP 7414083 U JP7414083 U JP 7414083U JP 7414083 U JP7414083 U JP 7414083U JP S59180463 U JPS59180463 U JP S59180463U
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
ceramic multilayer
separated
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7414083U
Other languages
Japanese (ja)
Other versions
JPH027483Y2 (en
Inventor
伯田　達夫
進 西垣
照沼　一彦
峰広 外崎
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP7414083U priority Critical patent/JPS59180463U/en
Publication of JPS59180463U publication Critical patent/JPS59180463U/en
Application granted granted Critical
Publication of JPH027483Y2 publication Critical patent/JPH027483Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のトリマーコンデンサを使用した基準発振
器の回路図、第２図は本考案に係るトリマーコンデンサ
の構成を説明するための断面図、第３図はそのトリマー
コンデンサの等−回路図、第４図は本考案の一実施例の
平面図、第５図はその実施例の等価回路図、第６図及び
第７図は他の実施例の平面図、第８図は第７図の実施例
の等価回路図である。 １０は第１導電パターン、１２．　１３．　１４゜１５
．１６は第２導電パターン、１７．１Ｂ。 １９．２０．２１は一方の接続用パッド、２３゜２４．
２５，２６．２７は他方の接続用パッド、２８．３０．
３２は導電層、２９は端子である。Fig. 1 is a circuit diagram of a reference oscillator using a conventional trimmer capacitor, Fig. 2 is a sectional view for explaining the configuration of the trimmer capacitor according to the present invention, and Fig. 3 is a circuit diagram of the trimmer capacitor. 4 is a plan view of one embodiment of the present invention, FIG. 5 is an equivalent circuit diagram of that embodiment, FIGS. 6 and 7 are plan views of other embodiments, and FIG. 8 is a plan view of the embodiment of the present invention. It is an equivalent circuit diagram of an example. 10 is a first conductive pattern; 12. 13. 14°15
．． 16 is a second conductive pattern, 17.1B. 19.20.21 is one connection pad, 23°24.
25, 26.27 are the other connection pads, 28.30.
32 is a conductive layer, and 29 is a terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 、　　　　　セラミック層の第１の面に形成された第１
の導電パターンと、上記第１の導電パターンとセラミッ
ク層を介して分離され、且つ上記第１の導電パ′　ター
ンに対向する互いに分離された複数の第２の導電パター
ンと、上記複数の第２の導電パターンが相互に電気的に
接続又は分離が可能に形成され、上記第１の導電パター
ンと上記複数の導電パターンにより形成されたトリマー
コンデンサを有するセラミック多層配線基板。, a first layer formed on the first surface of the ceramic layer.
a plurality of mutually separated second conductive patterns that are separated from the first conductive pattern via a ceramic layer and opposite to the first conductive pattern; A ceramic multilayer wiring board having a trimmer capacitor formed by the first conductive pattern and the plurality of conductive patterns, the conductive patterns being electrically connected or separated from each other.
JP7414083U 1983-05-18 1983-05-18 Ceramic multilayer wiring board Granted JPS59180463U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7414083U JPS59180463U (en) 1983-05-18 1983-05-18 Ceramic multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7414083U JPS59180463U (en) 1983-05-18 1983-05-18 Ceramic multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS59180463U true JPS59180463U (en) 1984-12-01
JPH027483Y2 JPH027483Y2 (en) 1990-02-22

Family

ID=30204237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7414083U Granted JPS59180463U (en) 1983-05-18 1983-05-18 Ceramic multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS59180463U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6416670U (en) * 1987-07-21 1989-01-27
WO2007125839A1 (en) * 2006-04-25 2007-11-08 Sumida Corporation Inverter circuit
WO2013108555A1 (en) * 2012-01-17 2013-07-25 ローム株式会社 Chip capacitor and method for manufacturing same
EP3929947A1 (en) * 2020-06-26 2021-12-29 Murata Manufacturing Co., Ltd. Method of fabricating a device comprising an electrical component with sub components connected using a plate to control an electrical parameter

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3231776B2 (en) * 1993-03-19 2001-11-26 富士通株式会社 Laminated circuit board

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4957363A (en) * 1972-10-04 1974-06-04
JPS50119815A (en) * 1974-03-08 1975-09-19
JPS51874U (en) * 1974-06-18 1976-01-06
JPS549867U (en) * 1977-06-24 1979-01-23
JPS5562721A (en) * 1978-11-02 1980-05-12 Tdk Electronics Co Ltd Laminated capacitor
JPS59132611A (en) * 1983-01-20 1984-07-30 日本電気株式会社 Capacitor composite substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS549867B2 (en) * 1972-09-20 1979-04-27

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4957363A (en) * 1972-10-04 1974-06-04
JPS50119815A (en) * 1974-03-08 1975-09-19
JPS51874U (en) * 1974-06-18 1976-01-06
JPS549867U (en) * 1977-06-24 1979-01-23
JPS5562721A (en) * 1978-11-02 1980-05-12 Tdk Electronics Co Ltd Laminated capacitor
JPS59132611A (en) * 1983-01-20 1984-07-30 日本電気株式会社 Capacitor composite substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6416670U (en) * 1987-07-21 1989-01-27
WO2007125839A1 (en) * 2006-04-25 2007-11-08 Sumida Corporation Inverter circuit
WO2013108555A1 (en) * 2012-01-17 2013-07-25 ローム株式会社 Chip capacitor and method for manufacturing same
JP2013168633A (en) * 2012-01-17 2013-08-29 Rohm Co Ltd Chip capacitor and manufacturing method of the same
US9859061B2 (en) 2012-01-17 2018-01-02 Rohm Co., Ltd. Chip capacitor and method for manufacturing the same
US10304633B2 (en) 2012-01-17 2019-05-28 Rohm Co., Ltd. Chip capacitor and method for manufacturing the same
US10777360B2 (en) 2012-01-17 2020-09-15 Rohm Co., Ltd. Chip capacitor and method for manufacturing the same
EP3929947A1 (en) * 2020-06-26 2021-12-29 Murata Manufacturing Co., Ltd. Method of fabricating a device comprising an electrical component with sub components connected using a plate to control an electrical parameter

Also Published As

Publication number Publication date
JPH027483Y2 (en) 1990-02-22

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