JPS59179489U - Pulse width modulation inverter - Google Patents
Pulse width modulation inverterInfo
- Publication number
- JPS59179489U JPS59179489U JP7199683U JP7199683U JPS59179489U JP S59179489 U JPS59179489 U JP S59179489U JP 7199683 U JP7199683 U JP 7199683U JP 7199683 U JP7199683 U JP 7199683U JP S59179489 U JPS59179489 U JP S59179489U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- switching pulse
- switching
- width modulation
- pulse width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のパルス幅変調インバータの結線図、第２
図ａ””＝ｅは第１図の動作説明用タイミングチャート
、第３図はこの考案のパルス幅変調インバータの要部の
結線図、第４図ａ ＝ ｉは第３図の動作説明用タイミ
ングチャートである。
２ａ〜２ｄ・・・第１〜第４トランジスタ、４・・・負
荷、９・・・制御部。Figure 1 is a wiring diagram of a conventional pulse width modulation inverter;
Figure a"" = e is a timing chart for explaining the operation in Figure 1, Figure 3 is a wiring diagram of the main parts of the pulse width modulation inverter of this invention, and Figure 4 a = i is a timing chart for explaining the operation in Figure 3. It is a chart. 2a to 2d...first to fourth transistors, 4...load, 9...control unit.
Claims (1)
ングパルス信号より低周波数の第２のスイッチングパル
ス信号を出力するパルス信号出力部と、前記各パルス信
号によりそれぞれスイッチ、ングし前記第１のスイッチ
ングパルス信号と前記第２のスイッチングパルス信号と
の差に基づく交流を負荷に出力する複数個のスイッチン
グ素子とを備えたパルス幅変調インバータにおいて、前
記第２のスイッチングパルス信号のデユーティファクタ
を制御する制御部を設けたパルス幅変調インバータ。a pulse signal output section that outputs a first switching pulse signal and a second switching pulse signal having a lower frequency than the first switching pulse signal; and a pulse signal output section that outputs a first switching pulse signal and a second switching pulse signal having a lower frequency than the first switching pulse signal; and a plurality of switching elements that output alternating current to a load based on the difference between the switching pulse signal and the second switching pulse signal, the control unit controlling the duty factor of the second switching pulse signal. Pulse width modulation inverter with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7199683U JPS59179489U (en) | 1983-05-13 | 1983-05-13 | Pulse width modulation inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7199683U JPS59179489U (en) | 1983-05-13 | 1983-05-13 | Pulse width modulation inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59179489U true JPS59179489U (en) | 1984-11-30 |
Family
ID=30202147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7199683U Pending JPS59179489U (en) | 1983-05-13 | 1983-05-13 | Pulse width modulation inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59179489U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011507463A (en) * | 2007-12-07 | 2011-03-03 | ヴァレオ システム ドゥ コントロール モトゥール | Circuit for controlling the current flowing through the electric control member or the voltage between the terminals of the electric control member |
-
1983
- 1983-05-13 JP JP7199683U patent/JPS59179489U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011507463A (en) * | 2007-12-07 | 2011-03-03 | ヴァレオ システム ドゥ コントロール モトゥール | Circuit for controlling the current flowing through the electric control member or the voltage between the terminals of the electric control member |
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