JPS6031189U

JPS6031189U - transistor inverter

Info

Publication number: JPS6031189U
Application number: JP12360083U
Authority: JP
Inventors: 真一石川
Original assignee: サンケン電気株式会社
Priority date: 1983-08-09
Filing date: 1983-08-09
Publication date: 1985-03-02

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の実施例に係わるインバータのブロック
図、第２図は第１図の制御信号形成回路を示すブロック
図、第３図は第２図の各部の状態を示す波形図、第４図
は第１図のカウンタ回路を詳しく示すブロック図、第５
図は第４図の各部の状態を示す波形図、第６図は本考案
の別の実施例に係わるインバータのベース制御回路を示
すブロック図、第７図は第６図のカウンタを詳しく示す
ブロック図、第８図は第６図の各部の状態を示す波形図
である。１〜６・・・トランジスタ、７・・・直流電源、８・・
・出力回路、９・・・制御信号形成回路、１０〜１２・
・・カウンタ回路、１３・・・クロックパルス発生口Ｌ
　１８．１９・・・カウンタ、２０．２１・・・ＮＯＲ
ゲート。FIG. 1 is a block diagram of an inverter according to an embodiment of the present invention, FIG. 2 is a block diagram showing the control signal forming circuit of FIG. 1, FIG. 3 is a waveform diagram showing the states of each part of FIG. Figure 4 is a block diagram showing the counter circuit in Figure 1 in detail;
The figure is a waveform diagram showing the states of each part in Fig. 4, Fig. 6 is a block diagram showing the base control circuit of an inverter according to another embodiment of the present invention, and Fig. 7 is a block diagram showing the counter in Fig. 6 in detail. 8 are waveform diagrams showing the states of each part in FIG. 6. 1-6...Transistor, 7...DC power supply, 8...
・Output circuit, 9... Control signal forming circuit, 10 to 12・
...Counter circuit, 13...Clock pulse generation port L
18.19...Counter, 20.21...NOR
Gate.

Claims

[Scope of claim for utility model registration]
and a second transistor, the conversion circuit configured to convert direct current to alternating current by operating the first and second transistors in reverse order with respect to each other; and controlling the first and second transistors. a rectangular wave control signal forming circuit that forms a rectangular wave control signal to , the rectangular wave control signal forming circuit and the first and '2
is provided between the base of the second transistor and counts the clock signal in response to one end kf of the square wave control signal, and when a predetermined count value corresponding to a time equal to or longer than the storage time of the second transistor is reached. A first base signal having a pulse width of a period from 1 to the other end of the rectangular wave control signal is supplied to the base of the first transistor; A second base signal having a pulse width of a period from the time when the clock signal is counted and reaches a predetermined count value corresponding to a time equal to or longer than the storage time of the first transistor to the other end of the negative phase signal is outputted to the second base signal. and a counter circuit that supplies the base of the second transistor.