JPS5917279A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5917279A
JPS5917279A JP57125694A JP12569482A JPS5917279A JP S5917279 A JPS5917279 A JP S5917279A JP 57125694 A JP57125694 A JP 57125694A JP 12569482 A JP12569482 A JP 12569482A JP S5917279 A JPS5917279 A JP S5917279A
Authority
JP
Japan
Prior art keywords
capacitor
leakage current
ta2o5
substrate
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57125694A
Other languages
Japanese (ja)
Inventor
Shinichiro Kimura
紳一郎 木村
Taijo Nishioka
西岡 泰城
Akira Haruta
亮 春田
Kiichiro Mukai
向 喜一郎
Akira Shintani
新谷 昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57125694A priority Critical patent/JPS5917279A/en
Publication of JPS5917279A publication Critical patent/JPS5917279A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to reduce sharply leakage current, to reduce the area of a capacitor, and to enhance the degree of integration of the device by a method wherein the device is constructed by depositing an insulating film having high permittivity on an N type Si substrate containing impurities in high concentration, and forming a metal electrode thereon. CONSTITUTION:After Ar gas of 5X10<-3>Torr is flowed to an Si substrate 1 and presputtering is perfomred, electric discharge of about 1.5kW power is generated under gas pressure of 5X10<-3>Torr of mixed gas of Ar and O2, and Ta2O5 of about 10nm thickness is deposited on the Si substrate 1. The measured value of interfacial level density (containing the influence of fixed electric charge in the film) QSS is obtained as such high density of 5X10<13>cm<-2> at Ta2O5 deposited as to form N type 10OMEGAcm resistance under the above-mentioned condition. The value of the leakage current to flow when the capacitor constructed by evaporating the metal electrode 3 of Al, etc. to constitute a confronting electrode on Ta2O5 2 formed by this way is used, and the respective leakage currents when a positive voltage and a negative voltage are applied are reduced to the small values as shown with the curves 4, 5, 6 respectively.

Description

【発明の詳細な説明】 本発明はタンタル酸化物、ニオブ酸化物、チタン酸化物
などの金属酸化物から成る高誘電率絶縁材料を用いたキ
ャパシタの構造に係り、特にそのリーク電流の小さいキ
ャパシタに好適な構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitor structure using a high dielectric constant insulating material made of a metal oxide such as tantalum oxide, niobium oxide, titanium oxide, etc., and particularly to a capacitor with a small leakage current. Regarding preferred construction.

タンタル酸化物などの高誘電率絶縁膜を用いた従来のキ
ャパシタでは、その電極にNiやCrなどの金属が用い
られていた。まだ、タンタル酸化物を用いた場合にはそ
のN極としてタンタル窒化物なども用いられている。し
かし、S j Ox膜に比べてリーク電流が大きいため
、従来大規模集積回路(LSI)などの高電界のかかる
キャパシタには関えないという欠点があった。
In conventional capacitors using high dielectric constant insulating films such as tantalum oxide, metals such as Ni and Cr are used for the electrodes. When tantalum oxide is used, tantalum nitride is also used as the N electrode. However, since the leakage current is larger than that of the S j Ox film, it has the disadvantage that it cannot be used in capacitors that are subject to high electric fields, such as conventional large-scale integrated circuits (LSI).

本発明の目的は、従来のこのような欠点を除去するため
のものであυ、かつ、耐圧の大きなキャパシタを作るこ
とによって、ダイナミック・ランダムアクセスメモリに
代表されるLSI中の微細なキャパシタへの高誘電率絶
縁膜の適用を可能にする新しい技術を提供することにあ
る。
The purpose of the present invention is to eliminate such drawbacks of the conventional technology, and by creating a capacitor with a high withstand voltage, it is possible to apply it to minute capacitors in LSIs such as dynamic random access memories. The purpose of this invention is to provide a new technology that enables the application of high dielectric constant insulating films.

不純物を高濃度に含むn形Si基板の上に高誘電率絶縁
膜を堆積させ、さらにその上に金属電極全形成したキャ
パシタで、リーク電流を測定した所、商誘篭−$絶縁膜
を金属ではさんだ従来構造のキャパシタに比べてリーク
電流が犬+ljに減少した。
A high dielectric constant insulating film was deposited on an n-type Si substrate containing a high concentration of impurities, and the leakage current was measured using a capacitor with metal electrodes formed entirely on it. Compared to a capacitor of conventional structure sandwiched between the two, the leakage current was reduced to +lj.

これは、金属電極に比べてStを用いると酸化膜と電極
とのショットキ障壁が大きくなるためと、シリコンと絶
縁膜の界面に重密度の界面準位が形成され、この界面率
イXTが電子を捕獲するだめにリーク電流が少なくなる
ものと考えられる。
This is because the Schottky barrier between the oxide film and the electrode becomes larger when St is used compared to a metal electrode, and a heavy-density interface state is formed at the interface between silicon and the insulating film, and this interface ratio XT is It is thought that the more leakage current is captured, the more the leakage current decreases.

実施例 以下、本発明の一実施例を第1図によシ説明する。本実
施例ではキャパシタの誘電体となる高誘電率絶縁膜とし
て、タンタル酸化物(’pa2Qs)を用いる。1ず、
第1図に示すように、不純物を高濃歴で含むn形Si1
にスパッタ法などを用いて’]:’a2Qs 2を堆積
させる。この時のスパッタには13.56MH2の几F
スパッタ装置を使用し、金属Ta板をターゲットとして
アルゴン(Ar)。
EXAMPLE Hereinafter, an example of the present invention will be explained with reference to FIG. In this embodiment, tantalum oxide ('pa2Qs) is used as a high dielectric constant insulating film serving as a dielectric of the capacitor. 1st,
As shown in Figure 1, n-type Si1 contains a high concentration of impurities.
']:'a2Qs 2 is deposited using a sputtering method or the like. At this time, the sputtering temperature was 13.56MH2.
Using a sputtering device, use argon (Ar) using a metal Ta plate as a target.

と酸素(02)の混合ガス中でTa2Q5を形成する反
応性スパッタ法を用いた。以下にスパッタ条件とその手
順を記す。Ta205を堆積させるn形Si基板は、ま
ず、水洗い・沸騰した硝酸中での表面酸化、稀フッ酸に
よる表面酸化物の除去という洗浄工程を通したものを使
用した。スパッタ装置にSi基板を配置し、5 X 1
0−”porrの高真空に引いた後、5 X 10−”
l’orrQArガスを流してプレスパツタと称し、タ
ーゲット表面の汚染層を除去するスパッタを20分程度
行う。プレスパツタ終了後、再び高真空に引き、Arと
02を流す。この時02の分圧は全圧の10〜20%程
度になるようにする。ガス圧が充分安定した後、放電を
開始する。この時、Arと02の混合ガス圧は5 X 
10−J7orrで行った。
A reactive sputtering method was used to form Ta2Q5 in a mixed gas of and oxygen (02). The sputtering conditions and procedures are described below. The n-type Si substrate on which Ta205 was deposited was first subjected to a cleaning process of washing with water, surface oxidation in boiling nitric acid, and removal of surface oxide with dilute hydrofluoric acid. Place the Si substrate in a sputtering device, 5 x 1
After pulling to a high vacuum of 0-”porr, 5 x 10-”
Sputtering is performed for about 20 minutes to remove the contaminant layer on the target surface, which is called pre-sputtering by flowing l'orrQAr gas. After the press sputtering is completed, the vacuum is again drawn to a high vacuum and Ar and 02 are flowed. At this time, the partial pressure of 02 should be about 10 to 20% of the total pressure. After the gas pressure becomes sufficiently stable, discharge begins. At this time, the mixed gas pressure of Ar and 02 is 5
It was performed at 10-J7orr.

放電は約1.5 kWのパワーで行い、約1100nの
’I’a2QsをSi基板−りに堆積させた。界面準位
密度(膜中の同定電荷の影響をも含む)Qssはn形1
0 、Q cmに上述の条件で堆積させた”l’ a 
2 Q sについて測定し、5 X 10”cm−2と
いう高密度のQ、ssを測定した。
The discharge was performed with a power of about 1.5 kW, and about 1100 nm of 'I'a2Qs was deposited on the Si substrate. The interface state density (including the influence of identified charges in the film) Qss is n-type 1
0, Q cm deposited under the above conditions.
2 Q s and a high density Q, ss of 5 X 10” cm −2 was measured.

このようにして形成しだTazQsの上にAtなどの対
向′#li、極となる金濁3を蒸着し、キャパシタを構
成する。このキャパシタを用いてリーク’fkt Ml
を測定したのが第2図であるう同図において、4は、第
1図のキャパシタ構造において、シリコン基板1上に、
まずAtを蒸着し、さらにTa2o52を堆積し、さら
にAt3を蒸着したキャパシタでのリーク電流を示す。
On the thus formed TazQs, an opposing layer of At, etc., and a gold cloud 3 serving as a pole are vapor-deposited to form a capacitor. Using this capacitor leak 'fkt Ml
In FIG. 2, 4 is the capacitor structure shown in FIG.
The leakage current in a capacitor in which At is first deposited, Ta2O52 is further deposited, and At3 is further deposited is shown.

また、5は第1図構造のキャパシタにおいて正電圧をか
けた時の、6は負電圧をかけた時のリーク電流を示す。
Further, 5 indicates a leakage current when a positive voltage is applied to the capacitor having the structure shown in FIG. 1, and 6 indicates a leakage current when a negative voltage is applied.

これより明らかなように、第1図構造のキャパ/りでリ
ーク電流が小さいことがわかる。また、第1表には第1
図構造のキャパシタにおける容量で獅δを示す。
As is clear from this, it can be seen that the leakage current is small in the capacitor having the structure shown in FIG. In addition, Table 1 also shows the first
Figure shows the capacitance of a capacitor with a structure.

容量の周波数分散ははとんどなく、醜δも小さいことが
明らかである。
It is clear that the frequency dispersion of the capacitance is negligible and the ugliness δ is also small.

第   1   衣 膜厚 1000人 電極面積 2 X 10−”cm2 上述のように本発明によれば、Ta205などの高誘電
率絶縁膜を用いたキャパシタのリーク電流を大巾に低減
することが可能である。このため、本発明を用いれば、
従来はリーク電流が大きいだめ、ダイナミックランダム
アクセスメモリのキャパシタとしての1更用が難しかっ
た高誘誘率絶縁fの適用が可能となりキャパシタの面積
を小さくすることができるだめ、集積度の大巾な向上が
できる効果がある。
1st coating film thickness: 1000 people Electrode area: 2 x 10-''cm2 As described above, according to the present invention, it is possible to significantly reduce the leakage current of a capacitor using a high dielectric constant insulating film such as Ta205. Therefore, if the present invention is used,
Conventionally, high dielectric constant insulation f, which was difficult to replace as a capacitor in dynamic random access memory due to its large leakage current, can now be applied, making it possible to reduce the area of the capacitor and greatly increasing the degree of integration. It has the effect of improving.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を用いたキャパシタの縦断面図、第2図
は第1図のキャパシタを用いて測定したリーク電流特性
、表1は比誘電率と誘電損失の周波数依存性を示す。 1・・・n形Si基板、2・・・高6岨率杷縁膜、3・
・・金手続補正書(方式) 事件の表示 昭和57 年特許願第325694  号発明の名称 半導体装置 補正をする者 、、、   1.、    751’lll’+、式会
111」   立  製  作  所1’、’  i’
2  ?’+   三   1)  勝  茂代   
理   人 氏  名   (7237)  ブ■〒 1:   薄
   1)  利   ′幸 、1補正命令σノ日付 
 昭和57年10月26日  ゛補正のχ−j象 明細書の図面の簡単な説明の欄 備Nトイ目内−容一 補正の内容 本願明細書第6頁第4行〜第6行[第2図は・・・依存
性ヶ示す。]を「第2図は第1図に示したキャパシタを
用いて測定して得られたリーク重加特性を示す曲線図で
ある。JKNI正する。
FIG. 1 is a longitudinal cross-sectional view of a capacitor using the present invention, FIG. 2 is a leakage current characteristic measured using the capacitor shown in FIG. 1, and Table 1 shows frequency dependence of dielectric constant and dielectric loss. DESCRIPTION OF SYMBOLS 1...n-type Si substrate, 2...high 6-concentration loquat film, 3...
・Written amendment for money procedure (method) Indication of the case Patent application No. 325694 of 1982 Name of the invention Semiconductor device Person making the amendment... 1. , 751'llll'+, Ceremony 111', 'i'
2? '+3 1) Shigeyo Katsu
Rito's name (7237) BU■〒 1: Usui 1) Ri'yuki, date of 1 correction order σ
October 26, 1980 ゛Amended χ-j Column for a brief explanation of the drawings in the specification Figure 2 shows the dependence. ] "Figure 2 is a curve diagram showing the leakage weighting characteristics obtained by measurement using the capacitor shown in Figure 1. JKNI correct.

Claims (1)

【特許請求の範囲】[Claims] 1、金属酸化物の高誘電率絶縁材料を誘電体とするキャ
パシタにおいて、電極材料の少なくとも一方が不純物濃
度の高いn形シリコンからなシ、前記高所−4絶縁材料
と前記n形7リコン膜の界(川に高ぞ度の界面準位を形
成することを特徴とする半導体装置。
1. In a capacitor whose dielectric is a metal oxide high dielectric constant insulating material, at least one of the electrode materials is n-type silicon with a high impurity concentration, and the above-mentioned high-place-4 insulating material and the above-mentioned n-type 7 silicon film are used. A semiconductor device characterized by the formation of high-resolution interface states in the field (river).
JP57125694A 1982-07-21 1982-07-21 Semiconductor device Pending JPS5917279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57125694A JPS5917279A (en) 1982-07-21 1982-07-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57125694A JPS5917279A (en) 1982-07-21 1982-07-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5917279A true JPS5917279A (en) 1984-01-28

Family

ID=14916385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57125694A Pending JPS5917279A (en) 1982-07-21 1982-07-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5917279A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198665A (en) * 1985-02-27 1986-09-03 Nec Corp Semiconductor device
US4853759A (en) * 1986-09-29 1989-08-01 American Microsystems, Inc. Integrated circuit filter with reduced die area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198665A (en) * 1985-02-27 1986-09-03 Nec Corp Semiconductor device
US4853759A (en) * 1986-09-29 1989-08-01 American Microsystems, Inc. Integrated circuit filter with reduced die area

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