JPS59172680A - Crt display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT device that displays double-width characters.

[Technical background of the invention and its problems]

In recent years, with the progress of Japanese language information processing technology.

High-level functions have been required of CRT display devices, which play an important role as a man-machine interface and are frequently used. In other words, it is not limited to displaying kanji characters, but also displays in color.

Examples include graph displays, fish loss displays, and double-width displays. By having these functions. Not only does it look good, but it also alerts the operator.

It has various effects.

Regarding the above-mentioned double-width display, the conventional processing method is as follows. That is, when trying to display double-width characters in the horizontal direction for a normal-sized character display, the firmware enlarges and generates the n-bit pixel/pixel turn that should be displayed once to 2n bits.

This is output and displayed as data.6 Figure 1 shows an example of double-width display. In the diagram.

An example is shown in which "1 kanji" is normally displayed in the section of line 0, column 0 (ad I/suoo') and "1 kanji" is displayed in double width across line 1, column 0.1.

According to the conventional processing method described above, the burden placed on software (firmware) is large.

Moreover, it has the disadvantage that it requires a considerable amount of processing time.

[Object of the invention].

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a CRT display device that achieves a single-width display using a small amount of hardware, thereby reducing processing time.

[A essential point of the invention]

The present invention applies double-width modification to each character section of a CRT display device of the type that has a character generator (not a video RAM type), and also enables the enable 0N10FF by turning on this modification bit.
When a bar-uniaron knock to control is provided at the front stage of the parallel-to-serial conversion circuit, and the above modification bit is ON.

The shift lt1 period is twice the normal display and one display data is displayed.

According to the present invention, since single-width display is realized by hardware, the burden on software is reduced and processing speed is increased.

[Embodiments of the invention]

The present invention will be explained in detail using the following five drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 21 is a display code memory (RM). The display code memory 2 stores code data of character information to be displayed in units of sections. Reference numeral 22 denotes a display modification memory (AM) for double-width display, in which data U]° is written at a position corresponding to the section address where single-width display is desired. The output of this display modification memory 22 is connected to a shift control circuit 24 via a free-lag float 23. A latch clock (LC) is supplied to a clock terminal (CK) of the flip-flop 23 from the outside. Moreover, this latch clock is connected to the latch terminal (LAT
CH) is also commonly given.

The shift control circuit 24 controls the shift operation (shift enable 0N10FF) of the parallel-to-serial conversion circuit 26, which will be described later.
) with inversion logic.

And gate;! 41. Inverter 242. It is composed of a Frisozo flop 243. The AND gate 241Fi obtains the set output of the flip-flop 230 and the reset output of the flip-flop 243, and supplies the result of the AND condition to the flip-flop 243. In addition, the other input terminal of this flip-flop 243 is connected to the inverter 2.
A basic clock (CLK) is supplied from the outside via 4. The output of this solve flop 243 is fed back to the AND gate 241 and is also supplied to the shift terminal (8H) of the parallel-to-serial conversion circuit 26. Parallel-serial conversion circuit 26
1 converts input display data into serial data and supplies it to a CRT monitor (not shown). A basic clock (CK) is obtained from the outside, and the period of this clock is made variable by the shift control circuit 24. 25 is a pattern ROM which converts the display code obtained from the display code memory 2 into pattern data and supplies it to the parallel-serial conversion circuit 26.

FIG. 3 is a timing chart showing the operation of the present invention. The numbers and symbols shown in the figures correspond to those in FIG. Also, in Figure 1, ``-'' indicates a normal display section, and B indicates a double-width display section.

Hereinafter, the operation of the present invention will be explained in detail using the timing shown in FIG.

First, the address (ADH) of the partition to be displayed is 1.
Display code memory 21 from the display control unit main body (not shown)
The 1-display modification memory 22 (two pairs are supplied in parallel; display code memory 2) stores the character code to be displayed in that section; Information is output. The code data obtained from the display character code memory 21 is NO! Turn RO
The data is supplied to M25, where it is converted into base turn data, and image data is output. The image data obtained here is converted into serial data via a parallel-to-serial conversion circuit 26.

Assume that a 1-bit flag for double-width display is set at the corresponding section position obtained from the 1-display modification memory 22. At this time, the flip-flop 23 operates as a latch clock (LC).
) with the advent of.

ON, the output of this flip-flop 23 is transmitted to the shift control circuit 24. At the same time, the output of the set ROM 2B is latched to the parallel-to-serial conversion circuit 26. The output of the flip-frog 23 is passed through the AND gate 241 constituting the shift control circuit 24 to the solilag flora f24.
3. A basic clock is supplied to the clock input terminal (CK) of the flip-frog 243 via the inverter 242, and the inverted output of the flip-frog is used as an output of the shift control circuit 24 as a terminal for shift enable of the parallel-to-serial conversion circuit 26. (SH). Therefore, this shift control circuit 24 functions as a switch for switching the shift enable 0N10Ii'F every time the basic clock (CLK) arrives, and as a result.

The shift period is doubled compared to the normal case.

This doubles the timing of serial data output to the -CRT monitor, making it possible to achieve the desired double-width display.

Although the present invention has been described by exemplifying a CRT display device, it can be similarly applied to devices that serially output slice information, such as facsimiles.

〔Effect of the invention〕

As described above, according to the present invention, single-width display is realized by hardware, so that the burden on software is reduced and the processing becomes more sophisticated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of double-width display on a display screen, and FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a dimming chart showing the operation of the present invention. 21--Display code memory (RM)-22--Display modification memory (AM)% 2.9--Flip float, 24--Shift control circuit, 25--Pattern RO
M, 26...Parallel-serial conversion circuit.

Claims (1)

[Scope of Claims] A first memory for displaying characters in units of sections and storing character codes for each section. For each section, a second memory for storing double-width modification instructions for the corresponding character; a flip-flop for latching the double-width modification information obtained from this second memory;
A shift control circuit that controls the shift cycle of the display r-evening using the modification information obtained through the float, and a shift control circuit that controls the shift cycle of 0N10FF by the output of this shift control circuit.
1. A CRT display device comprising: a parallel-to-serial conversion circuit that performs the following operations and outputs display data.