JPS59168996A - Method of writing control memory in computer - Google Patents

Abstract

PURPOSE:To prevent run away of a microprogram by writing data different from data to be written in specified plural check bits during the course of writing and detecting an error in reading control memory when interruption occurs in writing. CONSTITUTION:A check bit writing selecting section 5 attached to a check bit section 2 is connected to a CPU7 and connected also to output side of a check bit section reading register 4. Further, data section 1 and check bit section 2 of control memory CS are connected to a timing controlling section 6. When writing data, data for operation is written in 1-0, and data for parity check are written in 2-0, 2-1, in control memory CS in the first writing. When interrupted in the first writing, erroneous data are written in check bits 2-0, 2-1. Accordingly, errors of these two bits are detected when reading the control memory CS and operation by CPU is stopped. Operation is made similarly hereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of writing data to control memory in a computer.

(2) Background of the technology The control memory of a computer usually consists of a data section and a check bit section.The data section stores data necessary for calculations, while the check bit section stores information written to the data section. Some devices are equipped with an FCC (error detection and correction function) that writes data to detect whether or not the error is correct. Furthermore, some of these control memories write data into the control memory in parts. This is a method that divides the data part of one address (assuming that the data part consists of, for example, 4 bytes and 32 bits) into several sections (for example, 4 sections), and writes data to each section. It is. After writing to the data section, check information is written to the ECC. In a control memory that uses such a divided write method,
When writing the above-mentioned data, it is possible that a so-called interruption in storage may occur, in which data is written to some partitions but not to other partitions. When such an interruption occurs, in order for the central processing unit (CPU) to perform calculation processing correctly,
When reading data (or words) whose writing has been interrupted by the CPU, it is necessary to detect the fact that the writing has been interrupted.

(3) Prior art and problems Conventionally, in order to write data to the control memory illustrated above (the data field consists of 4 bytes for each address), the necessary data is written into the data field of each address. At the same time, error detection information for the data written at the address is written in the check bit section, and error detection is performed at the time of reading. As mentioned above, a check bit section of 7 to 8 bits is usually added to the 4-byte data section, and the bits that make up the check bit section serve as the parity of each byte in the data section. Bits are determined to serve as parity for multiple bytes.

However, in this conventional data writing method,
If there is an interruption in the writing of data to the control memory, when the CPU reads out the data for which the writing was interrupted, even though the data is erroneous, it is read out and operated without detecting an error. There is a problem with this.

(4) Purpose of the Invention The present invention has been made with attention to the above-mentioned problems, and its purpose is to eliminate the possibility of interruption in writing to the data section by writing to the check bits redundantly. An object of the present invention is to provide a method for writing data into a control memory in which an error can be detected when a word to be written is read even in such a case, thereby solving the above-mentioned conventional problems.

(5) Structure of the Invention In order to achieve this object, the present invention provides a write control circuit that divides data writing into a data part of a control memory having a data part and a check bit part. Until all areas are written, data different from the data to be written is written to a predetermined plurality of bits in the check bit section, and if writing to the data section is interrupted, The gist is that a 2-bit error is detected when a word to be written in the data section is read.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a data write control circuit for control storage to which the present invention is applied. In this figure, C8 indicates a control memory, and Re indicates a read register from which information written in the control memory is read. The control memory CS is, for example, 1-
0, 1-1.

1-2.1-3, a data section 1 having a 4-byte write section, and a check bit section 2 for parity checking the data written in the control memory C8K. Check bit part 2 is 2-0.2-1.2-2.2-
It is composed of three blocks (hereinafter referred to as check bits), and each check bit has a core of, for example, two bits incorporated therein.

The read register Re includes a data section read register 3 that reads data written in the data section 1 of the control memory C8;
It consists of a check bit section read register 4 for reading out data written in the check bit section 2. Data for various calculations are written in the data section 1 of the control memory C8 based on commands from the CPU 7, while data for parity checking is written in the check bit section 2. In the present invention, a check bit write selection section 5 is provided which determines which check pit should be written when data is written to the check pit section 2, and furthermore, this check bit write selection section 5 is provided. 5 is connected to the CPU 7 and also to the output side of the check bit section read register 4, so that data already written in the check bit section 2 of the control memory cs can be inputted as necessary. Furthermore, control memory C
The data section 1 and check bit section 2 of C.8 are connected to a timing control section 6, and the timing of writing to the control memory C8 is controlled by instructions from the timing control section 6.

Control memory C8 is controlled by such a data write control circuit.
A write is performed. In this data writing, I
In the writing of I white, calculation data is written to 1-0 in the control memory C8, and parity check data is written to 2-0.2-1.

For the 2nd to 4th writing, 2nd time 3rd time writing to 1-1 and 2-0.2-1 4th time writing to 1-2 and 2-0.2-2 1-3 and 2 -1.2-2.2-3 is impregnated.

The writing at each time is controlled by the timing control section 6, and the circuit of this timing control section 6 is shown in FIG. This timing control circuit transmits the timing signal TI for the timing signal TO11-1 for the byte 1-0 of the data section 1, the timing signal T2 for the byte 1-2, and the timing signal T3 for the 1-3, and controls the set of the transmitted signals. This indicates the number of writings at which the signal was sent.

Then, each timing signal to the data section in each write stage is the first write, TO=1, T1=0,
T2=0. T3=02nd write, TO=O, T1
=1. T2=O, T3=03rd write, 'I'O
=0. T1=O, T2=1. T3=04th write, TO=0. T1=O, T2=0. T3=1.

On the other hand, the timing control section 6 also transmits a write timing signal to the check bit section 2, but this write timing signal for the check bit is generated by the O as shown in FIG.
It is determined using the R (OR) gate 11°12.13.14. The OR gate 11 receives the timing signal T.
O, Tl, and T2 are input, and a write timing signal WECBO for check bits 2-0 is output. The above timing signals To, TI, and T3 are input to the OR gate 12, and a write timing signal W to the check bit 2-1 is input.
Output ECBI. The OR gate 13 also receives the timing signal T2. T3 is input and check bit 2
-2 write timing signal WECB2t- is output.

Further, the timing signal T3 is inputted to the OR gate 14, which outputs a write timing signal WECB3 to the check bits 2-3.

Figure 4 is a check mark)! 5 shows the circuit of the inclusion selection section 50.

This circuit has check pins) 2-0 and 2-1, respectively.
, 2-2, 2-3, and blocks 15, 16, 17, and 18. Block 15 is AND (and) game) 19.20 and O
It has an R gate 21, a FOR (exclusive or) gate 22. The data WC, BO, and TO to be written to the check bits 2-0 are input to the AND gate 19, and the AND gate 20 receives the read data RCKBO from the check bit section read register 4 and inverts the timing signal TO. The signal *TO is input. Ma7
The signals from each AND gate 19 and 20 are input to the OR gate 21, and the signal T1 of the signal from the OR gate 21 and the inverted timing signal T1 are input to the EOR gate 22.
is input and write data WCK to check bit 2-〇
BO is output. RCKBO is check bit 2-
0 is old data for WCKBO. Block 16 has AND gates 23 and 24, an OR gate 25, and an EOR gate 26. AND gate 2
3, the data WCBI and timing signal T1 to be written to the check bit 2-1 are input, and the AND
The read data RCKBI from the check pit read register 4 and the signal ITI obtained by inverting the timing signal 1'1 are input to the gate 24.

The signals from each AND gate) 23 and 24 are input to the OR gate 25, and the signal from the OR gate 25 and the timing signal T2tl - the inverted signal * are input to the EOR gate 26.
T2 inputs and write data W to check bit 2-1
CKBI is output. RCKBl is old data for WCKBI in check bits 2-1.

Block 1T includes AND gates 27 and 28, an OR gate 29, an EOR gate 30, and an OR gate 31. AND game) 27 has check bits 2-2
The data WCB2 to be newly written and the timing signal T2 are input to the AND gate 28, and the read data RCKB2 from the check bit section read register 4 and the timing signal T2t-inverted signal *T2 are input to the AND gate 28. The signals from each AND gate 27 and 28 are input to the OR gate 29, while the signals from the OR gate 29 and the signal from the OR gate 31 are input to the EOR gate 30. The included data WCKB2 is output.

Here, a signal *T2 obtained by inverting the timing signal T2 and a signal rate T3 obtained by inverting the timing signal T3 are input to the OR gate 31, and a predetermined selection signal is output. RCKB2 has W in check bits 2-2.
This is old data for CKB2. Block 18 is A
It has ND gates 32 and 33 and an OR gate 34.

The data WCB3 to be newly written to the check bits 2-3 and the timing signal T3 are input to the AND gate 32, and the data RCKB3 read from the check bit section read register 4 and the timing signal T3 are inverted to the AND gate 33. The signal rate T3 obtained is input. Signals from the AND gates 32 and 33 are input to the OR gate 34, and write data WCKB3 to check bits 2-3 is output. RCKB3 is old data for WCKB3 in check bits 2-3.

Next, a write operation performed using such a write control circuit will be explained. First, before writing to the control memory C8, reading is always performed to the read register Re. Then, due to the operation of the timing control section 6, TO, TI, T2 . T3 and as the sequence progresses, a commitment to control memory is made. In this write, when the write timing signal WECBi (i=0.1, 2.3) to each check bit is "0", no writing is performed to that check bit, and when it is 11', no writing is performed. conduct. Writing to the check bit section 2 at each stage is performed as follows.

First write (TO...1) From Figure 3, since WECBO and WECBI are '1' and WECB2 and WECB3 are '0', check bit 2-0.2-1 is left blank. write, 2-2.2-3 has no write.From Figure 4, WCKBO is WCBO
(bars indicate opposite polarity) and WCKBI is RCK
It becomes Bl. Therefore, data to be written is erroneously written to check bit 2-0, and erroneously written to check bit 2-1 by inverting the old value of that bit. On the other hand, regarding check bits 2-2, 2-3, it should be W and the old position should be reversed, but at the writing stage, it is not written as described above, so the correct data remains. .

Second write (TI...1) From Figure 3, WECBO and WECBI are "1'" and WECB2 and WECB3 are "0", so check bits 2-0.2-1 are Write, 2-2° 2-3 is no write. From Figure 4, WCKBO is RCKB.
O and Nashi, WCKBl becomes WCBI. Therefore, the old value (wrong data at the previous stage) is rewritten to check bits 2-0, and the data to be written is erroneously written to check bits 2-1. Other check bit 2-2.2
-3, WCKB2. WCKB3 each R
CKB2. It should become RCKB3 and the old position inversion writing should be performed, but at this writing stage, writing is not performed as described above.

3rd write (T2...1) From Figure 3, WECBO and WECB2 are "1'", and WECBI and WECB3 are "0'", so check) 2-0.2- 2 is writing, 2-1.2-3
is without soy sauce. From Figure 4, WCKBO is RCK
It becomes BO, and WCKB2 becomes WCB 2. Therefore, in check bits 2-0, the old value is inverted and written to become correct data, and in check bits 2-2, data that should be written is written in error. On the other hand, regarding check bits 2-1, 2-3, WCKBI and WCKB3 are respectively RCKBI.
.

Although it becomes RCKB3, it is not written at this stage.

4th Soaking (T3...1) From Figure 3, WECB 1, WECB 2, WEC
Since B 3 is 1'' and jD and WECBO are 0, check bits 2-1.2-2.2-3 are written.
2-0 is no writing. From Figure 4, WCKBl is RCKB 1, WCKB 2 is RCKB 2, WC
KB 3 becomes WCB 3. Therefore, in check bits 2-1 and 2-2, the old order is inverted and correct data is written, and in check bits 2-1 and 2-3, the data to be written is written correctly.

The above write operation is illustrated as below. To summarize this write operation, when TO=1 and T1=1, incorrect data is folded into check bit 2-0.2-1, T
When 2=1, correct data is written to 2-0, while incorrect data is written to 2-2. At T3=1, 2-1.2-2.
This means that 2-3 must be sworn to have correct data. In addition,
It was mentioned above that the data in the control memory should be read before writing to the control memory C8, but if an error occurs during this read, a fixed pattern is written and the data section 1 and check bit section 2 are initialized. (index). Thereafter, reading is performed again, and if an error occurs during reading, the storing sequence may be stopped.

A case will be considered in which the profile writing is interrupted while writing to the control memory C8 is being performed while writing to the check bit section 2 using the method described above.

If the process is interrupted at the first write, in this case, the interruption occurs only after data has been written to bytes 1-0 of the data section 10. In the check bit unit 2, from the table, the data of error υ is stored in check bits) 2-0.2-1, so when the control memory C8 is read, this 2-bit error is detected and the CPU Arithmetic operations stop.

If the process is interrupted during the second rounding, in this case, the interruption occurs with data written to the 10 bytes 1-0.1-1 of the data section. In the check bit unit 2, from the table, error data is written in check bits 2-0.2-1, so when the control memory C8 is read, this 2-bit error is detected and the arithmetic operation by the CPU is not performed. Stop.

If the writing is interrupted at the third time, in this case, data part 1 pie) 1-0, 1-1.1
An interruption occurs while data is being written to -2. In the check bit section 2, the check bit is displayed (check bit) 2-0.
The correct data is contained in the old position inversion write, but the error data from the second write remains in the check bit 2-1, and the check bit 2-2
Since erroneous data is also written in the control memory C8.
When this 2-bit error is detected, the arithmetic operation by the CPU is stopped.

In this way, when filling the control memory C8, the data section 1
Write to each pie) 1-0, 1-1.

1-2. Even if the writing is interrupted midway through the sequential writing to 1-3, it is possible to stop the CPU's arithmetic operation due to the erroneous data written to the check bit section 2. Prevent the microprogram from running out of control.

By the way, there is no writing interruption, and each byte 1-0 above
．． Let us consider the case where data is written to all of 1-1.1-2.1-3. In this case, check bit part 2 uses check bit 2-0.2-1.2-2.2 from the table.
Correct data is written to all -3. Therefore, when the control memory is read, unless there is another error, no erroneous error is detected and the arithmetic operation by the CPU continues.

(7) Effects of the Invention As explained above, according to the present invention, when the data commitment is divided into the data section of the control memory, the At this stage, we adopted a writing method in which data different from the data to be pledged was written to a plurality of predetermined check bits, so if there was an interruption in writing to the data section, an error would occur when reading the control memory. This was detected and it became possible to prevent the microprogram from running out of control.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a data write control circuit for control storage to which the present invention is applied, FIG. 2 is a timing control circuit diagram for controlling the operation of the data write control circuit, and FIG. A write/f-ming control circuit diagram, and FIG. 4 is a check bit write selection circuit diagram. 1...Data section 2...Check bit section 3
...Data section read register 4...Check bit section read register 5...Check bit write selection section 6...Timing control section C8...Control memory Re...Register Fig. 2 Fig. 3 Figure 4

Claims (1)

[Claims] In a write control circuit that divides data writing into the data part of a control memory that has a data part and a check pit part, in the middle of writing to all areas of the data part, the check pit part is If data different from the data to be written is written to a predetermined bit and writing to the data section is interrupted, an error is detected when the word to be written to the data section is read. A method for writing control memory in a computer, characterized by: