JPS59168659A - Lead frame for integrated circuit - Google Patents
Lead frame for integrated circuitInfo
- Publication number
- JPS59168659A JPS59168659A JP58042890A JP4289083A JPS59168659A JP S59168659 A JPS59168659 A JP S59168659A JP 58042890 A JP58042890 A JP 58042890A JP 4289083 A JP4289083 A JP 4289083A JP S59168659 A JPS59168659 A JP S59168659A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- alloy
- plating
- less
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85464—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は品質、信頼性及び経済性に優れた集積回路用リ
ードフレームを得んとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention aims to provide a lead frame for integrated circuits that is excellent in quality, reliability, and economical efficiency.
集積回路などの実装には各種の方式が実用化されている
が、半導体素子と外部回路の接続を導電基体からなるリ
ードフレームによル場合カ多い。第１図はその１例であ
り、チップ搭載部１、ワイヤボンディング部２及び外部
リード部３から構成され、例えばＦｅ−Ｎｉ合金、Ｃｕ
−Ｆｅ合金、Ｃｕ−８ｎ合金、Ｃｕ−Ｎｉ−８ｎ合金な
どの板状体をプレス成型しているものである。しかし機
械的、電気的及び熱的などの条件が満たされるならば上
記の合金に限ることなく任意の基材を使用することが出
来る。Various methods have been put into practical use for mounting integrated circuits, etc., but in many cases, the connection between a semiconductor element and an external circuit is made using a lead frame made of a conductive substrate. FIG. 1 shows one example of this, and it is composed of a chip mounting part 1, a wire bonding part 2, and an external lead part 3.
A plate-shaped body made of -Fe alloy, Cu-8n alloy, Cu-Ni-8n alloy, etc. is press-molded. However, as long as mechanical, electrical, thermal, etc. conditions are satisfied, any base material can be used without being limited to the above-mentioned alloys.
而し７てチップ搭載部と、これを外部と電気的に接続す
るワイヤーボンディング部を円滑に欠陥に行うためにこ
れらの表面にＡｕ又はＡｇをメッキするととが行われて
いる。なおこれは＋７−ドフレーム全面にメッキを施す
よりもリード搭載部とワイヤボンディング部のみの部分
メッキの方が経済的で望ましいとされている。In order to smoothly form defects in the chip mounting part and the wire bonding part for electrically connecting it to the outside, the surfaces of these parts are plated with Au or Ag. It is said that partial plating of only the lead mounting portion and wire bonding portion is more economical and desirable than plating the entire surface of the +7- card frame.
しかしＡｕメッキは側角性を有しＡｕ又はＡｔのボンデ
ィングワイヤとの溶接性及びチップとの鑞付性にも優れ
且つ長期の使用においても特に支障を生ぜず理想的な被
覆相であるが高価なことが欠点である。このため安価な
Ａｇメッキが普及しつつあるが、Ａｇは硫化などの表面
劣化をまねき易くリードフレームを保管する場合に細心
の注意を必要とする。更に致命的な問題は最も多量に普
及しているプラスチックＤＩＰ実装などにおいて、しば
しば故障をひきかこすＡｇマイグレーシ日ンである。こ
れは集積回路の実Ｊ１．ｌにおいて外気の浸度や汚染物
質の侵入などによって直流電圧印加部でＡｇのブリッジ
ができて知略をひきおこしてしまう。このため外気を完
全に遮断したり或はモールド外部にＡｇを出慣ないため
の多くの工夫や改善が必要とされている。However, Au plating has lateral properties and is excellent in welding properties with Au or At bonding wires and brazing properties with chips, and does not cause any problems even during long-term use, making it an ideal coating phase, but it is expensive. This is a drawback. For this reason, inexpensive Ag plating is becoming popular, but Ag tends to cause surface deterioration such as sulfidation, and great care must be taken when storing lead frames. An even more critical problem is Ag migration, which often causes failures in plastic DIP mounting, which is the most widely used method. This is a real integrated circuit J1. 1, a bridge of Ag is formed at the DC voltage application section due to the degree of infiltration of outside air or the intrusion of contaminants, causing problems. For this reason, many measures and improvements are needed to completely cut off the outside air or prevent Ag from coming out of the mold.
又Ａｇ ＋ Ａｕはチップ搭載部に使用する半田と極め
て易溶性であシ、半田溶接中に、その基体金属が露出し
て接合性を著しく阻害する。そのため経済的には可及的
に薄いＡｕ、Ａｇの被偵力≦望まれながら実際上にはＡ
ｇで１〜５μ、Ａｕ −ｃ’ モ０．５〜２μの如き厚
メッキを行っているものである。Furthermore, Ag + Au is extremely easily soluble in the solder used for the chip mounting portion, and its base metal is exposed during solder welding, significantly impairing bonding properties. Therefore, economically, the detection power of Au and Ag is as thin as possible ≦ Although desired, in reality A
Thick plating is carried out, such as 1 to 5 μm in g and 0.5 to 2 μm in Au-c′.
本発明はかかる現状に鑑み鋭意研究を行った結果なされ
たものであυ、リードフレームとしての特性と経済性を
両立できる集積回路１ノードフレームを見出したもので
ある。即ち不発８Ｊ４ｔまチップ搭載部、ワイヤビンデ
ィング部及び外部リード部から措成される４電基体にお
いて、少くとも上記チップ搭載部とワイヤデンディング
部の伺れか一方又は両方の表面にＰｄ又はＰｄ合金（ｒ
−被彷したことを特徴とするものである。The present invention has been made as a result of intensive research in view of the current situation, and has resulted in the discovery of an integrated circuit one-node frame that can achieve both characteristics as a lead frame and economical efficiency. That is, in a four-electronic base made up of a chip mounting part, a wire binding part, and an external lead part, Pd or a Pd alloy is applied to the surface of at least one or both of the chip mounting part and wire binding part. (r
- It is characterized by wandering.
ＰｄはＡｇ、 Ａｕの中間コストにもかかわらず耐食性
を有し、且つ集積回路実装に袂求される前記の接合性に
おいて極めて優れている。又高融点金属であシ基体、例
えばＣｕとの拡散反応をおこすことがないのでＡｕ、Ａ
ｇの如く拡散劣化障害の心配は全くなく且つ半田に易は
難いので素地露出障害をおこし難い。現用のボンディン
グワイヤとの接合にも勿論優れている。更にＡｕｌＯ代
シに作業性に優れた貴金属ボンディングワイヤとしてＰ
ｄ又はＰｄ−Ａ、などの線が普及しはじめたが、同種金
属のデンディングであるため冶金学的にも全く問題なく
信頼性の高い接合が出来る。Although Pd is intermediate in cost between Ag and Au, it has corrosion resistance and is extremely excellent in the bonding properties required for integrated circuit packaging. In addition, since it is a high melting point metal and does not cause a diffusion reaction with a substrate such as Cu, Au, A
There is no fear of diffusion deterioration problems like in g, and since it is not easy to solder, it is difficult to cause substrate exposure problems. Of course, it is also excellent in bonding with current bonding wires. In addition, P is used as a noble metal bonding wire with excellent workability compared to AlO.
Wires such as d- or Pd-A have started to become popular, but since they are made of the same metal, highly reliable bonding can be achieved without any metallurgical problems.
又Ａｇの如きマイグレーシ日ンの心配が全くないのでプ
ラスチックＤＩＰなどでも安心して使用出来る。Also, there is no worry about migration like Ag, so it can be used with peace of mind even with plastic DIPs.
本発明においてはＰｄＯ外Ｐｄ合金例えばＮ１分６０チ
以下を含むＰｄ、Ｎｉ合金、Ｃｏ分６０係以下を含むＰ
ｄ−Ｃｏ合金、Ａｇ分７０壬以下を含むＰｄ−Ａｇ合金
、Ｃｕ分２０係以下を含むＰｄ−Ｃｕ合金、Ａｕ分５０
係以下を含むＰｄ−Ａｕ合金などが実用される。これら
の合金は前記のＰｄの特性を本質的に保有し、且つ合金
化に伴う軽済効果を有すると共に接合性や加工性などの
馴〉ト的効果を附与する。In the present invention, Pd alloys other than PdO, such as Pd containing 60% or less of N, Ni alloys, and Pd containing 60% or less of Co.
d-Co alloy, Pd-Ag alloy containing Ag content of 70 parts or less, Pd-Cu alloy containing Cu content of 20 parts or less, Au content of 50 parts or less
Pd-Au alloys containing Pd-Au alloys and the like are in practical use. These alloys essentially possess the above-mentioned properties of Pd, and have a lightening effect associated with alloying, as well as imparting familiar effects such as bondability and workability.
このＰｄ又はＰｄ合金はリードフレームの全面に施すこ
とは可能であるが、チップ搭載部又は？ンディング部の
少くとも一方に神覆すればよいがテップの搭載をエポキ
シ樹脂又はイミド糸樹脂の接着剤で行う場合は、必ずし
もＰｄ、 Ｐｄ合金は不要でありがンディング部のみで
十分である。他方ボンディング技術の改善によシ基体上
にディレクトボンディングを行う場合は、チップを前記
の導電接着剤や鑞付けする搭載部のみで十分である。This Pd or Pd alloy can be applied to the entire surface of the lead frame, but it can be applied to the chip mounting area or the entire surface of the lead frame. It is sufficient to overturn at least one side of the binding part, but if the tip is mounted using an adhesive such as epoxy resin or imide resin, Pd or Pd alloy is not necessarily required, and only the binding part is sufficient. On the other hand, if bonding technology is improved and direct bonding is performed on the substrate, it is sufficient to mount the chip with the aforementioned conductive adhesive or solder.
又Ｐｄ又はＰｄ合金を被接するには任意の方法で行えば
よく、覗見メッキ、化学メッキ又はス・母ツタリングな
どが特に有利である。又その被恍厚については実用上０
．５μ以上であればリードフレームとしての特性を満足
しうるものである。Further, any method may be used to apply Pd or a Pd alloy, and plating, chemical plating, sputtering, etc. are particularly advantageous. In addition, the thickness of its perdition is practically 0.
．． If it is 5 μ or more, the characteristics as a lead frame can be satisfied.
次に本発明の実施例について説明する。Next, examples of the present invention will be described.
実施例（１）
Ｏ１３２ｔのＣｕ−ｏ、 ３ ｅ４８μ合金からなるリ
ードフレームの表面に常法によシ脱脂及び活性化を行っ
た後、ラックメッキ法によυ０，２５μのＮｌメッキを
行い、次いで０，７５μのＰｄ ｉメッキして本発明リ
ードフレームをえた。Example (1) After degreasing and activating the surface of a lead frame made of O132t Cu-O, 3E48μ alloy by a conventional method, Nl plating of υ0.25μ was performed by rack plating method, and then A lead frame of the present invention was obtained by plating with 0.75μ PdI.
なおＮｌメッキしてＮｉＳＯ４浴を用い５ Ａ／ｄｍ
によシ行い、Ｐｄメッキは繕田中貴金属（株）製パラ
デックスＭＳ浴（６０℃）を用い１． ＯＡ７ｄｍ”に
て行った。In addition, Nl plating was performed using a NiSO4 bath at 5 A/dm.
1. Pd plating was performed using a Paradex MS bath (60°C) manufactured by Tatetanaka Kikinzoku Co., Ltd. I went on "OA7dm".
又比較のためにＰｄメ、キに代えて中性シアン浴によ、
！ｌ） ０．７５μのＡｕメッキ（比較例（１））と、
シアン浴による３μのＡｇメッキ（比較例（２））を夫
々行って比較例リードフレームをえた〇
斯くして得た本発明品及び比較例品についてビンディン
グ性、半田付は性及びマイグレーシロン性を夫々測定し
た。その結果は第１表に示す通シである。Also, for comparison, a neutral cyan bath was used instead of Pd and Ki.
! l) 0.75μ Au plating (comparative example (1)),
Comparative lead frames were obtained by performing 3μ Ag plating (Comparative Example (2)) using a cyan bath. The binding properties, soldering properties, and migration properties of the products of the present invention and comparative products thus obtained were evaluated. Each was measured. The results are shown in Table 1.
（１） ボンディング性
４００℃×５分大気中にて加熱後２５μＡｕ線で超音波
熔接して、その接合強度を測定した。(1) Bonding property After heating in the air at 400° C. for 5 minutes, ultrasonic welding was performed using a 25 μAu wire, and the bonding strength was measured.
なお２０本連続してビンディングした平均値である。Note that this is the average value of 20 consecutive bindings.
（２）チップ半田付は性
４００℃×５分大気中にて加熱後、３５０℃の９５％Ｐ
ｉｉ−５係Ｓｎ半田浴中に５秒浸漬して演れ面積を比較
した。５本の平均値である。(2) For chip soldering, heat at 400°C for 5 minutes in the air, then 95% P at 350°C.
Section ii-5 The test pieces were immersed in a Sn solder bath for 5 seconds and the warp areas were compared. This is the average value of 5 pieces.
（３） 外部端子との半田付は性
４００℃×５分大気中に加熱後、更に９０チＲＨＸ６０
℃Ｘ１．０００ｈｒのエージング処理を行って、２４０
℃の４０４ Ｐｂ−６０％ ８ｎの半田浴に５秒浸漬し
て濡れ面積を測定した。(3) For soldering with external terminals, heat in the air at 400°C for 5 minutes, then heat for another 90° at RHX60.
℃×1.000hr aging treatment, 240
The wetted area was measured by immersing it in a 404 Pb-60% 8N solder bath at a temperature of 5 seconds.
（４） マイグレーシ日ン試験
２本のリード線を切υ出し、２咽間隔で、定性２紙上に
固定し、６０℃×９０係ＲＨのデシケータ−中に入れ１
５Ｖの直流電圧を加えて１００Ｈｒ放置後、メグオーム
メーターで極間抵抗を測定した。(4) Migration test Cut two lead wires, fix them on qualitative paper at two intervals, and place them in a desiccator at 60°C x 90% RH.
After applying a DC voltage of 5 V and leaving it for 100 hours, the resistance between the electrodes was measured using a megohmmeter.
第 １ 表
実施例（２）
４２憾Ｎ１−Ｆθ（０，０２５ｔ）製リードフレームを
常法によシ、脱脂及び活性化を行った後、Ｎ ｉ ｄ
２浴會用いて全面に０．１μのＮｉストライクメッキを
行った。次いで常法のスポットメッキマシーンによりチ
ップ搭載部とボンディング部に１μノ８０ Ｐｄ−２Ｏ
Ｎ１合金メッキを行って本発明リードフレームをえた。Table 1 Example (2) After a lead frame made of 42 N1-Fθ (0,025t) was degreased and activated by a conventional method, N i d
Ni strike plating of 0.1 μm was applied to the entire surface using two baths. Next, 80 Pd-2O of 1 μm was applied to the chip mounting area and bonding area using a conventional spot plating machine.
A lead frame of the present invention was obtained by performing N1 alloy plating.
なおメッキ浴は日進化成製ＰＮＰ −ｓ ｏで平均電流
密度５ Ａ／ｄｍ２とした・
又比較のためにＰｄ−Ｎ１メッキに代えて２μのＡｇメ
ッキ（比較例（３））及び５μのＡｇメッキ（比較例（
４） ） ’に夫々行った以外はすべて実施例（２）と
同様にして夫々比較例リードフレームをえた。The plating bath was PNP-so manufactured by Nikka Seisai, with an average current density of 5 A/dm2.For comparison, 2μ Ag plating (comparative example (3)) and 5μ Ag plating were used instead of Pd-N1 plating. Plating (comparative example (
4)) Comparative example lead frames were obtained in the same manner as in Example (2) except that steps 1 and 2 were carried out respectively.
斯くして得た本発明品及び比較例品について６０℃Ｘ９
０％ＲＨＸ２日のエージング処理を施した後、デンディ
ング性及びチップ半田付は性を測定した。その結果は第
２表に示す通シである。The products of the present invention and comparative products thus obtained were heated at 60°C
After aging at 0% RHX for 2 days, the bending properties and chip soldering properties were measured. The results are shown in Table 2.
（１） ボンディング性
２５μＡｕ線を超音波熔接した後前記と同様に接合強度
を測定した。(1) Bonding properties After ultrasonically welding 25 μAu wires, the bonding strength was measured in the same manner as above.
（２） チップ半田伺は性
搭載部に９５４ Ｐｂ−８ｎ中に０８φＣｕ線を重ねて
、４００℃×３０秒間加熱した。Ｃｕ線を引張り試駆し
て接合強度を測定した。(2) For chip soldering, a 08φ Cu wire was layered in 954 Pb-8n on the mounting part and heated at 400° C. for 30 seconds. The bonding strength was measured by pulling a Cu wire.
第 ２ 表
第１表及び第２表よシ明らかの如く本発す」１ノードフ
レームによれば従来の！Ｊ−ＩＦ７Ｌ／−ムヨシテンデ
イング性及び半田付は性等において優れていることを示
した。Table 2 As is clear from Tables 1 and 2, according to the 1-node frame, the conventional! J-IF7L/- It was shown that the binding properties and soldering properties were excellent.
以上詳述した如く本発明によれば従来Ｐｄは水素吸蔵な
どによシ脆性なポーラスな被覆材であるといわれていた
ものをリードフレームに第１」用して侵れた特性を発揮
せしめ且つ経済的に極めて有利なリードフレームをうる
等工業的に有用なものである。As detailed above, according to the present invention, Pd, which was conventionally said to be a porous covering material that is brittle due to hydrogen absorption, is used in the lead frame to exhibit properties that have not eroded. It is industrially useful, such as producing economically extremely advantageous lead frames.
図面は集積回路用リードフレームの１秒０を示す平面図
である。
Ｊ・・・チップ搭載部、２・・・ワイヤビンディング部
、３・・・外部リード部。The drawing is a plan view showing 1 second 0 of a lead frame for an integrated circuit. J...Chip mounting part, 2...Wire binding part, 3...External lead part.
Claims (1)
から構成される導電基体からなる集積回路用リードフレ
ームにおいて、少くとも上記チップ搭載部とワイヤボン
ディングの何れか一方又は両者の表面にＰｄ又はＰｄ合
金を被υしたことを特徴とする集積回路用リードフレー
ム。In an integrated circuit lead frame consisting of a conductive substrate comprising a chip mounting part, a wire bonding part, and an external lead part, at least one or both of the chip mounting part and the wire bonding may be coated with Pd or a Pd alloy. A lead frame for integrated circuits that is characterized by its υ shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58042890A JPS59168659A (en) | 1983-03-15 | 1983-03-15 | Lead frame for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58042890A JPS59168659A (en) | 1983-03-15 | 1983-03-15 | Lead frame for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59168659A true JPS59168659A (en) | 1984-09-22 |
| JPS6349382B2 JPS6349382B2 (en) | 1988-10-04 |
Family
ID=12648623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58042890A Granted JPS59168659A (en) | 1983-03-15 | 1983-03-15 | Lead frame for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59168659A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0250146A1 (en) * | 1986-06-16 | 1987-12-23 | Texas Instruments Incorporated | Palladium plated lead frame for integrated circuit |
| JPH04211153A (en) * | 1990-02-26 | 1992-08-03 | Hitachi Ltd | Semiconductor package and lead frame |
| US5675177A (en) * | 1995-06-26 | 1997-10-07 | Lucent Technologies Inc. | Ultra-thin noble metal coatings for electronic packaging |
| US6150712A (en) * | 1998-01-09 | 2000-11-21 | Sony Corporation | Lead frame for semiconductor device, and semiconductor device |
| JP2001152122A (en) * | 1999-11-22 | 2001-06-05 | Sumitomo Bakelite Co Ltd | Electrically conductive resin paste and semiconductor device using the same |
| US6245448B1 (en) * | 1988-03-28 | 2001-06-12 | Texas Instruments Incorporated | Lead frame with reduced corrosion |
| US6261402B1 (en) | 1997-10-24 | 2001-07-17 | Sony Corporation | Planar type lens manufacturing method |
| US6521358B1 (en) * | 1997-03-04 | 2003-02-18 | Matsushita Electric Industrial Co., Ltd. | Lead frame for semiconductor device and method of producing same |
| US7285845B2 (en) | 2005-04-15 | 2007-10-23 | Samsung Techwin Co., Ltd. | Lead frame for semiconductor package |
| DE4431847C5 (en) * | 1994-09-07 | 2011-01-27 | Atotech Deutschland Gmbh | Substrate with bondable coating |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005057067A (en) * | 2003-08-05 | 2005-03-03 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5219076A (en) * | 1975-08-05 | 1977-01-14 | Fujitsu Ltd | Production method of semiconductor package |
-
1983
- 1983-03-15 JP JP58042890A patent/JPS59168659A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5219076A (en) * | 1975-08-05 | 1977-01-14 | Fujitsu Ltd | Production method of semiconductor package |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0250146A1 (en) * | 1986-06-16 | 1987-12-23 | Texas Instruments Incorporated | Palladium plated lead frame for integrated circuit |
| US6245448B1 (en) * | 1988-03-28 | 2001-06-12 | Texas Instruments Incorporated | Lead frame with reduced corrosion |
| JPH04211153A (en) * | 1990-02-26 | 1992-08-03 | Hitachi Ltd | Semiconductor package and lead frame |
| DE4431847C5 (en) * | 1994-09-07 | 2011-01-27 | Atotech Deutschland Gmbh | Substrate with bondable coating |
| US5675177A (en) * | 1995-06-26 | 1997-10-07 | Lucent Technologies Inc. | Ultra-thin noble metal coatings for electronic packaging |
| US6521358B1 (en) * | 1997-03-04 | 2003-02-18 | Matsushita Electric Industrial Co., Ltd. | Lead frame for semiconductor device and method of producing same |
| US6261402B1 (en) | 1997-10-24 | 2001-07-17 | Sony Corporation | Planar type lens manufacturing method |
| US6150712A (en) * | 1998-01-09 | 2000-11-21 | Sony Corporation | Lead frame for semiconductor device, and semiconductor device |
| JP2001152122A (en) * | 1999-11-22 | 2001-06-05 | Sumitomo Bakelite Co Ltd | Electrically conductive resin paste and semiconductor device using the same |
| JP4543460B2 (en) * | 1999-11-22 | 2010-09-15 | 住友ベークライト株式会社 | Conductive resin paste and semiconductor device using the same |
| US7285845B2 (en) | 2005-04-15 | 2007-10-23 | Samsung Techwin Co., Ltd. | Lead frame for semiconductor package |
| KR100819800B1 (en) | 2005-04-15 | 2008-04-07 | 삼성테크윈 주식회사 | Lead frame for semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6349382B2 (en) | 1988-10-04 |
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