JPS59167122A - Input and output buffer - Google Patents

Abstract

PURPOSE:To reduce the area which a buffer occupies and to enhance the number of degrees of freedom for design by arranging a unit MOSFET set, which consists of two P-channel MOSFETs having common source and drain and two N- channel MOSFETs having common source and drain, in an input/output shared part of the input/output buffer. CONSTITUTION:In respect to difference of the device arrangement of this buffer from that of a conventional buffer, an input circuit part and an output circuit part are constituted as an input/output shared part 30 in this buffer. This input/ output shared part 30 is used though this input/output buffer is used as only an input circuit or an output circuit, and this part 30 includes plural P-channel MOSFETs 31 and N-channel MOSFETs 32 smaller than MOSFETs used as a pair of P-channel and N-channel MOSFETs for output, and two P-channel MOSFETs and two N-channel MOSFETs, at least, of these plural MOSFETs have common source and drain contacts 34 and 37 respectively, and source electrodes, drain electrodes, and gate electrodes of MOSFETs other than these MOSFETs have independent contacts respectively.

Description

[Detailed description of the invention] Unexploded qu, complementary MO8 field effect transistor (hereinafter C
The present invention relates to a cover for integrated circuits (denoted as MO8) and special VC logic integrated circuits.

Recently, as logic integrated circuits have become more highly integrated, desired logic can be transferred to on-chip VC in order to reduce development man-hours and shorten development time.
To realize this, gate arrays using the master slice method have become widely used in VC. In a gate array, a desired complete logic configuration is achieved by connecting elements that are prepared in advance and arranged in an array with metal wiring.

Therefore, even the process of forming elements can be carried out in common, and various logic integrated circuits can be obtained just by changing the metal wiring.

For example, in a CMUS gate array, P channel-N channel MO8F called internal logic cell array part
Cells arranged in a full array of ET pairs are arranged in the central part of the chip VC, and a desired logic is constructed in this part. The transmission and reception of signals between the input and output of the chip,
This is done via an input/output cover and fur corresponding to each pad and provided between the pad and the internal logic cell array portion. The input/output circuit and fur include input protection circuits and MO-8FETs with large drive capacity, which are indispensable for the signal interface between the internal logic cell array and the outside of the chip.

Input/output buffers are arranged corresponding to all signal pads, so that any signal pad can be used as an input terminal, an output terminal, or an input/output bidirectional terminal. i.e. input by the logic function of the chip,
Even if the positions of the pads serving as output or input/output bidirectional terminals are different, each position v can be used as an input buffer, an output buffer, or a buffer for both input and output.

Conventionally, input/output covers and fur have only a simple logic function used as an interface circuit as described above, and their logic function is almost limited to the circuit shown in Figure N1, so the and as shown in Figure 3 VC rζ
A convenient element arrangement and element configuration is adopted for this purpose.

In FIG. 1 VC, 1 is an input protection circuit, 2.3 is an inverter circuit, and 2 and 3 constitute the entire input circuit portion. Case 4 is an inverter circuit, and 5 is a NAND circuit! , 6 are NO circuits, and 4.5 and 6 constitute an output circuit portion. Furthermore, 7 is a P-channel MO8FET for output.

8 is an output N-channel MO8FET. That is, a signal inputted to the input signal line 10 from outside the chip passes through two stages of the input protection circuit 1 and the inverter 2.3 of the input circuit section, and is inputted from the input signal line 11 to the internal logic cell section. In addition, the signal output of the internal logic cell part is the output signal line 12.
is input to the output circuit part ON AND circuit 5 and NOR
The signal is inputted to a pair of output MOSFETs through a circuit 6, and outputted from an output signal line 13 to the outside of the chip. Control signal line 14
The control signal for making the output signal line 13 full height impedance is received from all the internal logic cell parts.Thereby, the input signal line IO and the output signal line 13 are commonly connected, and the signal pad KM is connected, and both input and output It can be used as a direction terminal.

Figure 2 shows the conventional element arrangement 1 of the passenger cover 7a shown in Figure 1.
In Figure 0, 15 indicates the entire area of the input/output buffer and signal pad, 16 indicates the signal pad, 1
7 is an input protection circuit part, 18 is an input circuit part, 19 is an output circuit part, 20 is an output P-channel MO8, l;
"B'l', 21 is N-channel MO8F'E for output
It is T. The input protection circuit section 17 corresponds to the IVC shown in FIG. 1, the input circuit section 18 corresponds to the inverter 2.3 shown in FIG. 1, and the output circuit section 19 corresponds to the inverter 4, shown in FIG.
The output MO8F'ET20.21 corresponds to the NAND circuit 5, NOR, and circuit 6, and the output MO8F'ET20.21 corresponds to the M(JSFET
Compatible with 7.8.

As is clear from the figure, the input circuit section and the output circuit section are arranged separately. Therefore, if the input/output buffer is used for both input and output, all the sections shown in Figure 2 are used, but if the input/output buffer has only one function, input or output, the sections shown in the section are used. Not used. For example, when used as an input, the output circuit part is wasted, and conversely, when used as an output, the input circuit part is wasted.

In addition, as shown in Fig. 3, the input circuit section of ttC Fig. 2 is composed of an inverter circuit, and the P-channel MO8F
The gate electrodes of the N-channel MO8F'ET paired with ET are connected in common in advance. In other words, in Figure 3, 22 is the P channel MO.
8FET, 23 is an N-channel MO8-FET, 24 is a common gate, and 25 is a source and a drain. This common gate? Has fcP channel-Nf channel M08F
Each pair of ET corresponds to the MOSFET vc that constitutes the innocent circuits 2 and 3 of FIG. As shown in FIG. 4, the inverter circuit uses the common gate 28 of the P-channel MO8FET 26 and the N-channel MO8FET 27 as input, and the source/drain connection point 29 of the MOSFET pair.
The output is

Note that NAND circuits and NOR circuits also use this common game) M(
Since it can be constructed based on a JSFET pair, it goes without saying that the output circuit portion in FIG. 2 also has the same construction as in FIG. 3.

However, in order to configure inverter circuits, NAND circuits, etc. in this way, P-channel MO8-FET
Sharing the gate of the N-channel MO8FET and the N-channel MO8FET means lowering the degree of freedom of the device.

That is, when trying to configure a special logical function, it is often impossible to design it.

That is, an element arrangement as shown in FIG. 2 or an element configuration as shown in FIG. 3 has drawbacks such as poor element usage efficiency and difficult design.

Furthermore, as the logic functions included in the VC and chip become more complex, the input/output buffer (VC) is also required to have various logic functions. Also, the number of elements in each of the output path sections is increased, which has the disadvantage that the area occupied by the input/output cover and fur increases.

It is an object of the present invention to provide an input/output cover and fur having a novel element configuration that eliminates such drawbacks.

The invention is based on a plurality of P channels - N channels 'N (
An internal logic cell portion in which cells consisting of JSFET pairs are arranged in an array is arranged at the center of the chip, and a plurality of input/output pads are arranged at the periphery of the chip.
Correspondingly, in an input/output buffer of a logic integrated circuit, in which an input/output cover and a fur are arranged around the input/output pad and between the internal logic cell part, the input/output buffer has a pair of P channels. An output MOSFET pair consisting of an N-channel MO8FET and a plurality of smaller pairs of P-channel and N-channel MOSFETs.
FET pigeon 1 includes an effective logic MO8FET pair, and at least two P-channel and N-channel MO8FETs in the logic MOSFET pair each have a common source.
The MO8li'ET has a drain contact, and the other source electrode, drain electrode, and gate electrode of the MO8li'ET each have an independent contact.

Next, the present invention will be explained with reference to all the drawings.

FIG. 5 is a diagram showing the entire layout of elements of an embodiment of the input/output buffer of the invention. The equivalent part to Figure 2 is.

The difference from FIG. 2 is that the fc symbol used for VC in FIG. 2 is shown with a dash "'°" in its entirety. This is the input/output common part, and the output P channel - N channel MOSFET vs. the MOSFET used for VC and the smaller P channel MO
8FET and an N-channel MO-8PET, the plurality of M (at least two P-channel MO8FETs and two N-channel MO8F in JSFET)
ET has common source and drain contacts, respectively.
The other source electrodes, drain electrodes, and gate electrodes of the MO8FET are cut out so that they each have independent contacts.

Figure 6 shows the multiple MO-8Fs in the input/output common part of Figure 5.
In FIG. 0, which is a diagram showing an example of the arrangement and configuration of a unit MOSFET pair that is a part of an ET, 31 is a P-channel MO8FET, 32 is an N-channel MO-8FET,
33 is the gate electrode of the P-channel MO8FET, 34 is the common source/drain electrode of the P-channel MO8FET, 35 is the source or drain electrode of the P-channel MO8FET, 36 is the deep-channel MO8F'ET (D gate electrode, 37 is the N-channel, Common source/drain electrode of MO-8FET, 38 is N-channel MO8FET
It is clear from Figure 0 that K is the source or drain electrode of
The two P-channel MO-8FETs and the N-channel MO-8FET each have a common source/drain terminal, but even with this element configuration, it is the same as the element configuration shown in Figure 3, as well as the VC1 inverter circuit. , there will be no problem with VCs forming NAND circuits or NOR circuits.

In addition, Fig. 7 shows a Schmitt circuit used as an input circuit in special cases.
and 42 is a P-channel MO8FET, 43°44.4
5 and 46 FiN channel MO8FET, 47 is an input signal line that receives the signal from the input maintenance circuit.

Reference numeral 48 denotes an input signal line for outputting the output of the Schmitt circuit to the internal logic cell section.

By the way, for example, a system like the one shown in FIG.

Conventionally, when a circuit is required as an input circuit, a third
As shown in Figure rC, the VC input circuit part has only the elements for two inverters, so it is not possible to create a Schmitt circuit, but in the input/output buffer-VC of the present invention, the input/output common part The unit MO8FE shown in Figure 6 is
Since multiple T are prepared, two unit MOSFE
Using T-pairs is easier to make than VC.

As mentioned above, the unit MOSFE is made up of a pair of four P-channel MO8FETs and two N-channel MO8FETs with a common source and drain.
By arranging the T pair in the input/output common part VC of the input/output buffer, it is better to arrange the MOSFET in the input/output common part of the input/output buffer.
P-channel MO8-FET and N-channel MO8FE
The gates of the T gates are connected to a common VC, and compared to the K type, the area is smaller, and the degree of freedom in design is higher, and various logic configurations can be easily made.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the logic circuit included in the input/output cover and fur, Fig. 2 is a TV layout diagram showing the conventional element arrangement of the input/output cover 7a in Fig. 1, and Fig. 3 is the input of the conduit 2 Fig. A layout diagram showing the element configuration of the circuit section, FIG. 4 is a circuit diagram showing an 0MO8 inverter circuit, FIG. 5 is a layout diagram showing an example of an inventive element arrangement of an input/output buffer, and FIG. FIG. 7 is a layout diagram showing the element configuration of the input/output common section shown in the figure, and a circuit diagram showing the seamit circuit of the FiCMU 8 shown in FIG. 15'... Input/output cover, fur and signal pad area, 16'... Signal pad, 17'...
...Input protection circuit part, 20'...P-channel MO8-FET for output, 21'...N-channel MO8-FET for output. -30...Input/output common part, 31...Channel embroidery 8E, BT, 32...N
Channel M08FET, 33...Gate electrode of P channel MO8FET, 34...Common source/drain electrode of P channel MO8FET, 35
・・・・・・Source or drain electrode of P channel MO8F'ET, 36...N channel M)=S
FET gate electrode, 37...N channel M
O8-FET common source/drain electrode, 38...
...Source or drain electrode of N-channel MO8FET. ＃ l Figure 2 Koku No. 31￥I 4th item 5 Figure 6 Concave Figure 7

Claims (1)

[Claims] An internal logic cell portion in which cells each consisting of a reasonable number of P-channel and N-channel MO8FET pairs are arranged in an array is arranged in the center of the chip, and a plurality of outputs The input/output pad V
An input/output cover of a logic integrated circuit, in which an input/output buffer is disposed around the input/output pad and between the internal logic cell portion, corresponds to C, and the input/output buffer is connected to a pair of P channels. An output MO8-FBT pair consisting of an N-channel MO8FET pair and a logic MO8-FET pair consisting of a plurality of smaller P-channel-N channel 1 VIO8FE'r pairs, including at least two in the logic MOSFET pair. P channel M
08F'ET and two N-channel MO8F'ETs each have a common source/drain contact, and the MO8
An input/output cover characterized in that the other source electrode, drain electrode and gate electrode of the FET each have an independent contact point, 7
a