JPS59165454A - Lateral type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high current amplification factor and to improve the integration of a semiconductor device by forming a high impurity buried layer formed inside a dielectric isolating insulating film near the periphery of an emitter region except a side opposed to a collector region, thereby improving a carrier transfer efficiency. CONSTITUTION:An N<+> type buried layer 12 and a dielectric isolating oxidized film 11 are projected to the side of an island 6 as compared with a conventional example so that an interval between the outer periphery of a P type emiter 2 and the inner edge of the layer 12 is substantially uniform at the three sides except the side opposed to the collector 1 of the emitter 2. Accordingly, the distance between the adjacent two sides of the side opposed to the P type collector 1 of the emitter 2 and the layer 12 is largely reduced as compared with the conventional example. As the results, the current amplification factor can be increased without losing the withstand voltage.

Description

[Detailed Description of the Invention] (Field of Application) The present invention relates to a lateral type semiconductor device, and in particular, a lateral type semiconductor device that can realize a high current amplification factor and increase the degree of integration by reducing the required island area. The present invention relates to semiconductor devices.

(Prior Art) FIG. 1 is a plan view of a conventional high voltage PNP transistor, and FIG. 2 is a sectional view thereof.

As is clear from the figure, the p collector 1 is made of K, dielectric isolation oxide film (Sin, ) 11 in order to satisfy the predetermined collector breakdown voltages (collector-paste breakdown voltage BVCBO and collector-emitter breakdown voltage BVCEO). It is formed with a sufficient distance from the n-type buried layer I2 and the p emitter 2, which are formed under the inner wall pressure.

Furthermore, since the p emitter 2 generally does not require emitter breakdown voltage, it is formed close to the n0 buried layer. n
+Pace 6 is a high impurity concentration diffusion region for taking out an electrode from the single crystal region 6, that is, the pace region.

In Fig. 1, 2 is a p emitter, 4 is a collector electrode (field plate type), 7 is an emitter electrode (field plate type), and 8 is a pudge page blank (
5i(h), 9 is base X pole V-do, 13 is polycrystalline SI
It is #.

Conventionally, methods for increasing the current amplification factor of a transistor include (1) increasing the collector length (first Lc);
(2) Reduce the distance between the p collector 1 and the p emitter 2. (3) Reduce the depth of the island.

Methods such as these are known.

Increasing the collector length Lc increases the length facing the emitter and improves the transport efficiency of minority carriers.
Current amplification factor increases.

However, since it is necessary to maintain the collector breakdown voltage at a predetermined value, the distance between the n0 buried layer 12 and the p collector 1 (for example, L in FIG.
i) cannot be reduced below a certain limit. Therefore, this method has the disadvantage that the required surface area of the single crystal island is large (which becomes a hindrance to an improvement in the degree of semiconductor integration).

The distance between the p-collector 1 and the p-emitter 2, that is, the base width, decreases by l''\. Since the charge transport efficiency is improved, the current amplification factor is increased. However, on the other hand, the collector
This causes a problem in that the emitter-to-emitter breakdown voltage (B VcBo ) decreases, making it impossible to satisfy a predetermined breakdown voltage.

When the depth of the island is made shallow, the minority carriers injected from the emitter 2 toward the bottom of the single-crystal island, that is, toward the n0 buried layer, are transferred from the n0 buried layer 12 (high p degree region) at the bottom of the island. It is reflected by the diffused electric field pressure toward the base region of the koto crystal sI6, and reaches the collector direction pressure.

Therefore, the distance traveled by the minority carriers taking the above-mentioned path becomes smaller by l'', that is, the base width in this direction becomes smaller, so that the current amplification factor increases.

However, in this case, there is a drawback that the distance between the p collector 1 and the n0 buried layer 12 at the bottom of the island becomes small, the electric field strength in that part increases, and the withstand voltage decreases. Also, as a countermeasure to this problem, it is possible to make the island shallower in the p emitter portion, but this requires a large number of manufacturing steps and is not economical.

(Purpose) The purpose of the present invention is to effectively improve the transport efficiency of minority carriers injected from the emitter, thereby achieving a smaller size and an improved degree of integration while maintaining the same performance as the conventional one. The purpose of the present invention is to provide lateral semiconductor devices such as pnp (pnp) transistors and thyristors.

(Summary) In order to achieve the above object, the present invention includes a highly impurity buried layer provided inside the insulating film for rust electrical isolation around the emitter region except for the side facing the collector region. This creates a diffused electric field from the buried layer toward the base region (island) K, which reflects minority carriers injected from the emitter in a direction other than the collector direction and directs them toward the collector, thereby improving carrier transport efficiency. The feature is that it is configured to improve the current amplification factor and obtain a higher current amplification factor.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 is a plan view of a high voltage lateral PNP transistor, which is an embodiment of the present invention. N: 1'6, its cross-sectional view is the same as in Fig. 2.

Similarly to FIG. 1, the polycrystalline 31 is
A striped p-collector 1 is formed near the center of the single-crystal island 6 that is insulated from the p-collector 1.
A p emitter 2 is formed in parallel with.

In the five unselected sides facing the collector of the p emitter 2, the distance between the outer periphery of the p emitter 2 and the inner edge of the n0 buried layer I2 is approximately uniform. The embedding layer 12 and the dielectric isolation oxide film 11 are made to protrude toward the island 6 compared to the conventional example shown in FIG.

In other words, in this first example, the planar shape (pattern) of the single crystal Si island 6 is not a rectangle (including a square, the same applies hereinafter), but the two adjacent vertices of the conventional rectangular single crystal Si island 6. , are made to protrude inward in a rectangular shape so that the whole has an octagonal shape.

Therefore, the distance between the two sides of the p emitter 2 adjacent to the side facing the p collector 1 and the h+embedding N+2 is #I
As is clear from the comparison between FIG. 3 and FIG. 1, the amount has been significantly reduced compared to the conventional example.

It is obvious that there is no need to state this again, but the distances between the p collector 1, the n buried layer 12, and the p emitter 2 are set to the extent necessary to achieve a predetermined withstand voltage. .

Furthermore, as can be seen from FIG. 2, the n0 buried layer 11 is
It is also formed at the bottom of the single-crystal sI island 6, and the distance from the p collector 1 is kept as necessary in this direction.

As a result, the current amplification factor can be increased without impairing the withstand voltage.

In one specific example of this embodiment, the resistivity of the single-crystal Si island n-region 6 is 20 to 25 Ω·F, and the diffusion depth of pNl, 2 is 5 μm.

In addition, as shown in FIG. 6, the distance between the p collector 1 and the p emitter 20 is 55 μm, the distance between the p collector 1 and the n buried layer is 65 μm, and the distance between the p emitter 2 and the force + buried layer 12 is 55 μm. The distance is approximately 5 μm.

Note that the p collector length is 155 μm, and the p emitter length is 60 μm.
It is μm.

As can be seen from FIG. 2, the electrodes 4 of the p-type collector 1 are fused across the respective junctions via the padgebage four sio and membrane 8. As is well known, this is what is called a feed plate, and is a means of reducing electric field concentration near the surface of the collector junction 81 by electric field effect and improving withstand voltage.

The electrode 7 of the p-emitter 2 similarly has a field plate structure, but this prevents a channel generated on the surface of the single crystal 81 between the collector and the emitter by an electric field effect. In this way, by applying a temperature limit under the emitter electrode to prevent the formation of a channel, the withstand voltage can be further improved.

The buried layer 12 is a channel stopper.

The concentration of the n0 buried layer 12 is preferably low in order to reduce the electric field strength at the end of the channel and increase the withstand voltage. On the other hand, in order to increase the diffusion electric field at the interface with the n base (i.e., single crystal 81 islands) 6 and to efficiently reflect the holes injected from the emitter, the concentration of the n buried layer I2 must be Bigger is better.

Considering the above, the n+ buried layer 1 in the specific example
The impurity concentration of 2 was selected to be approximately 5×10 cm.

The current amplification factor of the pnp lateral transistor of this practical example was distributed in the mouth region shown in FIG.

That is, according to this embodiment, the conventional p
That of the np lateral transistor (range A in Figure 4)
We were able to achieve a higher current amplification factor compared to the previous model.

Also, compared to the conventional one, as mentioned above, the n+ buried layer 1
2 and the electrical isolation oxide film 11 were made to protrude toward the inside of the single-crystal Si island 6, thereby making it possible to reduce the occupied area. This corresponds to an area reduction of 20-50%.

On the other hand, in order to achieve a current amplification factor comparable to that of the conventional one, the collector length can be further reduced, and the large area can be reduced accordingly. In this case, the area will be reduced by 65-50%.

FIG. 5 is a diagram showing a planar pattern of a high-voltage lateral PNP transistor according to a second embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line v--v.

The p collector 1 is formed on a diagonal line of the center of the single crystal St island 6. Furthermore, the p emitter 2 is located at such a position that the side facing the p collector 1 is parallel to the opposite side of the collector 10, and the other surface is close to the n buried layer while maintaining a predetermined distance. and formed into a shape.

That is, in this embodiment, since the -p collector 1 is arranged in the diagonal direction of the rectangular island, the collector can be made the longest for a certain size of the island, and the collector efficiency can be improved. On the other hand, since the p emitter 2 is surrounded by the n buried layer 12 at a short distance,
The above-described mechanism can improve carrier transport efficiency.

As a result, a high current amplification factor can be obtained.

In the typical numerical example of the second embodiment shown in FIG. 5, the p collector length is 85 μm, the p emitter length is 50 μm, and the other dimensions are the same as in the first embodiment.

The pnp) transistor of each of the above embodiments has a breakdown voltage of 380~
420 ■, and the current amplification factor hFE was 20-50. On the other hand, the same performance p of the conventional structure as shown in Fig.
Compared to np lateral transistors, we were able to achieve a 27-40% reduction in single-crystal surface sludge.

The present invention is not limited to the above-described embodiments, and those skilled in the art will readily recognize that various modifications can be made. The present invention can also be applied to a lateral type thyristor in which an n-layer is formed in the collector, and as a result, the ignition current and FVD can be reduced due to an increase in the current amplification factor.

(Effects) According to the present invention, the transport efficiency of minority carriers injected from the emitter can be improved, so compared to conventional lateral semiconductor devices, it is possible to integrate smaller lateral semiconductor devices with the same performance. You can increase the degree, while
If the dimensions are about the same, a larger current amplification factor can be achieved.

Further, according to the present invention, a lateral type semiconductor device with a high degree of integration can be obtained without changing the conventional manufacturing process.

[Brief explanation of the drawing]

Figure 1 is a plan view of a conventional pnp lateral transistor.
FIG. 2 is a cross-sectional view thereof, FIG. 6 is a plan view of the pnp lateral transistor of the first embodiment of the present invention, FIG. 4 is a comparison diagram of the current amplification factor between the conventional structure and the first embodiment, and FIG. FIG. 5 is a plan view of a pnp lateral transistor according to a second embodiment of the present invention, and FIG. 6 is a sectional view taken along line v--■ in FIG. 1...p collector, 2...p emitter, 6
...n+ base, 6...single crystal Si island, 8
・・・Oxide film, 12...n 10 buried area, 13・
...Patent attorney representing polycrystalline Si Michihito Hiraki Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] (]) - A conductive type single crystal island is embedded in a polycrystal through a dielectric film, and has a pair of main surfaces, one of which has only a polycrystalline region, Further, on the other main surface, a small amount (both the single crystal island and the dielectric film are exposed, and within the single crystal island, at least an emitter region and a collector region of opposite conductivity types are provided so as to be exposed on the other main surface. , - In a semiconductor device in which a single crystal island internal pressure is provided in contact with the dielectric film so that a small portion (at least a portion) of the conductivity type high concentration semiconductor region is exposed on the other main surface, the high concentration semiconductor region is Extending below the plurality of opposite conductivity type semiconductor regions, a part of the emitter replacement faces the collector region, and on the other main surface, the distance from the emitter region to the high concentration semiconductor region is A lateral type semiconductor device characterized in that the distance from the collector region to the high concentration semiconductor region is set to be smaller than the distance from the collector region to the high concentration semiconductor region.(2) The shape of the single crystal island on the other main surface is rectangular, and A patented lateral type semiconductor device characterized in that an emitter region is provided at the top.