JPS60245248A - Semiconductor ic - Google Patents

Abstract

PURPOSE:To contrive the improvement of low voltage element characteristic and high withstand voltage element characteristic by removing the decrease of the former characteristic and the loss of the latter characteristic by a method wherein a projection which does not reach the surface of an element is formed immediately under the impurity diffused region in the element-forming region separately from a groove to isolate elements. CONSTITUTION:In the titled device having a dielectric-isolated structure that element-forming regions have been insulated from each other by an insulation dielectric, projections 9 which do not reach the surface of the element are formed immediately under the impurity diffused layer in the element-forming region separately from the groove to isolate the elements. For example, in formation of an element isolating groove by anisotropic etching with alkali in the case of n-p-n transistors, a groove shallower than the isolating groove is formed at the same time by utilizing an etching window narrower than the isolating groove, and the projection 9 is formed at the bottom of an n type island region 3. This manner reduces the thickness 7a of the n<-> layer undr an emitter region 4 and then enables the improvement of low voltage element characteristic and the removal of unnessary work in the high withstand voltage element to be attained without decreasing the withstand voltage characteristic because the thickness 7b of the n<-> layer under a base region end 8 is not changed.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a dielectric isolation structure. n
Using a transistor (pn) as an example, it had a II structure as shown in FIG. In FIG. 1, 1 is a polycrystalline silicon substrate that holds separated element formation regions, 2 is an oxide film that disconnects the element formation regions from each other, and 3 is an n-type element formation region (hereinafter referred to as an n-type island). 4 is an emitter, 5 is a paste, and 6 is a channel stopper placed in the wall and bottom of the n-type island region to eliminate the influence of the potential of the substrate 1 on the inside of the n-type island region. It also has a collector buried layer that reduces collector resistance.

Dielectric component 1111. In conventional integrated circuits, n
In order to make the depth of the mold island region uniform, the depth is determined by the elements in the integrated circuit that require the greatest depth, such as lateral SC holes with low on-resistance, straw elements with high breakdown voltage, and the like. On the other hand, in the transistor shown in No. 11, the thickness 7 of the n-layer near the emitter has a large effect on the collector resistance of the transistor and the characteristics at the time of large collector current or low collector voltage, and therefore It is desirable to make this layer thinner, but due to the aforementioned considerations with other elements, the depth of the n-type island region tends to become deeper. could not be avoided.

In addition, when the element alone is inferior, the breakdown voltage of the transistor in the structure shown in FIG. 1 is determined mainly by electric field concentration at the base region end m8. It is necessary to increase the distance 1ljit between the wall and bottom portion of the island region and the end portion 8 of the base region to a certain extent, but at this time, in a place where electric field concentration does not occur, for example, directly under the emitter, the distance 1ljit between the wall and bottom portions of the island region and the end portion 8 of the base region must be increased to a certain extent. This resulted in the distance being larger than necessary, resulting in waste in terms of characteristics.

(Objective of the Invention) The object of the present invention is to eliminate the shortcomings of integrated circuits with dielectric isolation structures, particularly the deterioration of low voltage device characteristics and the waste of high voltage device characteristics, and to provide an integrated circuit with improved characteristics. The purpose is to provide circuits.

(Structure of the Invention) A semiconductor integrated circuit of the present invention has a dielectric isolation structure in which a plurality of element formation regions are insulated from each other by an insulating dielectric. Separately, a convex portion that does not reach the element surface is formed directly under the impurity diffusion layer in the element forming region.

(Example) Next, an example of the present invention will be described with reference to Eko.

FIG. 2 (al, bl is a plan view and a cross-sectional view of the A-A' plane of an embodiment of the present invention.
, (bl represents the structure of the present invention) transistors, and in the figure, numerals 1 to 6 and 8 indicate the same parts θ■ as in FIG. 1. Further, 7a indicates a thickness of n layers below the emitter region 4, and 7b indicates a thickness of n layers below the end portion 8 of the base region. 9 is a convex portion formed on the belly of the n-type island region, and in this example, an etching window narrower than the separation groove is used to create the cord molecule P#Pm by anisotropic etching with alkali. Separation grooves and shallow trenches can be formed at the same time.

This depth can be freely controlled depending on the width of the window.

7a is adjusted to such an extent that the breakdown voltage of the transistor does not fall below the required value of Pk.

As a result of the above, a semicircular element is obtained in which, in addition to the hooks for separating the elements, the convex part 9 that does not reach the element surface is formed directly under the impurity diffusion layer in the element formation region, and the 78 part is made smaller.
Since 'ybs is not consumed, it is possible to improve the characteristics of the low voltage element without completely degrading the withstand voltage characteristics, and also to eliminate waste in the withstand voltage element.

FIG. 3(a) is a plan view of the second embodiment of the present invention and a cutaway view of the B-H' plane.
As shown in Figures (a) and (b), the convex part 10 at the bottom of the n-type island region is formed to have a flat part facing the emitter. , the improvement in characteristics is superior to that of the first embodiment, but there is an additional problem that the element forming region 10 cannot be formed at the same time as the isolation trench, which increases the number of steps. ), (b) and Figure 4 (a)
, (b) is a characteristic diagram showing the transistor characteristic sound collector voltage-current characteristic of the embodiment of the present invention and the conventional example of FIG. 1; Note that the base current is assumed to be constant at 0.2 mA. In Fig. 4, 11 is the transistor characteristic according to the conventional method,
At the rise of the collector current, there is a part with a gentle slope due to the thick n-~ under the emitter.On the other hand, 12 shows the characteristics of the first or second embodiment, but the slope is quite steep. This shows that only the part 13 between the two convoluted glands where the no-tuchinku was applied has been improved. Correspondingly, the elongation of h at large currents is also improved.

In the above description, an npn (npn) transistor was taken as an example, but the present invention is not limited to this, and the same can be applied to a pnp transistor.

Furthermore, it goes without saying that the same effect can be achieved not only with transistors but also with diodes, lateral type elements, and the like.

(Effects of the Invention) As explained above, according to the present invention, the disadvantages of integrated circuits with a l!%jt body isolation structure, particularly the deterioration of low voltage element characteristics and the waste of high voltage elements, are eliminated, and these disadvantages are eliminated. A semi-isomorphic integrated circuit with improved characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional transistor with a dielectric all-over structure, FIG. 2 (al, lb) is a plan view and cross-sectional view of a first embodiment of the present invention, and FIG. b) is a plan view and a sectional view of the second embodiment of the present invention, and FIG.
It is a characteristic diagram which shows the collector voltage-current characteristic of a conventional example and an Example of this invention. 1... Polycrystalline silicon substrate, 2... Oxide film, 4... Emitter, 5... Base, 6... Channel stopper. , 7, 7a, 7b
...Distance between the diffusion layer and the bottom of the n-type island region, 8...
... End of base region, 9.10 ... Convex part of element formation region 1, 11 ... Device characteristics of conventional method,
12...Characteristics of the cord of the present invention. Figure 1 Beam Figure 2 Figure 3

Claims (1)

[Claims] In a semiconductor integrated circuit having a dielectric isolation structure in which a plurality of element formation regions are insulated from each other by an insulating vj% body, a convex portion that does not reach the element surface is added to the element formation region in addition to a rule that separates the elements. A semiconductor integrated circuit characterized in that it is formed under a surface of impurity-diffused waste within the semiconductor integrated circuit.