JPS59165448A - Complementary semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the latchup withstand strength and the stability of the operation by interposing a wiring region between an element row made of P- channel transistors and an element row made of N-channel transistors, and using the elements of both sides interposed at both sides of the wiring region to execute the logic function. CONSTITUTION:Each element row is composed of N-channel or P-channel elements so that both the N-channel and P-channel elements are not contained within the same element row. The N-channel element rows are disposed so that two rows of the N-channel elements are linearly symmetrically disposed to the center line of the element rows. The P-channel element rows are similarly disposed. To execute the logic function, the P-channel elements of the first row and the N-channel elements of the second row left side, the N-channel elements of the second row right side and the P-channel elements of the third left side are combined for use. The fourth and later rows are similarly combined. According to this structure, the distance between the N-channel region and the P-channel region is 5-20mum in the conventional device, but can be much increased, for example, to approx. 100-200mum in this device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary semiconductor integrated circuit device, and particularly to a device employing a master slice method.

“Background of the Invention and Problems Thereof” A master slice type semiconductor integrated circuit device is a semiconductor integrated circuit device in which a large number of basic cells each consisting of a plurality of elements are fabricated on a semiconductor substrate in advance, and the wiring layers and connection holes are changed to create the desired structure. It aims to obtain the circuit operation of the circuit, and has the feature that it can relatively easily meet the demands for circuits with new functions.In other words, the semiconductor chip created by the process before forming the metal wiring is Since it is common to all functional circuits,
Adopting the above method shortens the development period, reduces manufacturing costs, and enables high-mix, low-volume production. FIG. 1 shows a general example of a complementary semiconductor integrated circuit device using the master slice method.

That is, in this semiconductor integrated circuit device, the top of the semiconductor chip includes an N channel region IN, a P channel region 1p1, a wiring region 2, an input/output terminal, and an input/output circuit region 31c51). FIG. 2 shows a cross-sectional structure taken along the line (■) in FIG. 1. In other words, the base substrate 4, the well 5 having the opposite conductivity type as the base, the well potential settings as the pole 6, the N channel transistor's source 7, the gate 8, the drain 9, and the base substrate potential settings! These are the source 11, gate 12, and drain 713 of a polar 10° P-channel transistor. A problem with this rigid 0MO8 structure is a latch-up phenomenon. This is a parasitic bipolar transistor 1 due to noise etc.
This is a phenomenon in which 4.15 conductors conduct and excessive current flows. It is known that increasing the distance between the P-channel region and the N-channel region is a good way to increase the breakdown voltage leading to latch-up, but this has the drawback of increasing the chip area and increasing costs.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a complementary semiconductor integrated circuit device suitable for the master slice method.

[Summary of the invention]

According to the present invention, an element array consisting of P-channel transistors and an element array consisting of N-channel transistors are arranged across a wiring area, and when realizing a logic function, the elements on both sides of the wiring area are connected. used.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained compared to the conventional technology. That is, since the distance between the P channel region and the N channel region can be increased, the latch-up breakdown voltage can be improved and more stable operation can be obtained.

[Embodiments of the invention]

FIG. 3 shows an example of a gate array type large-scale integrated circuit to which the present invention is applied, and FIG. 4 shows a cross-sectional structure along the line indicated by 3 in FIG. 3. Each device column is composed of N-channel devices or P-channel devices 9, and the same device column does not include both N-channel devices and P-channel devices. In the N-channel element row, two rows of N-channel transistors are arranged symmetrically with respect to the center line of the element row. The same applies to the P-channel element array. The key to realizing logical functions is
The element array is used as follows. That is, the P-channel device in the first row and the N-channel device on the left side of the second row, and the N-channel device on the right side of the second row and the P-channel device on the left side of the third row are used in combination. The same applies to the fourth and subsequent columns. In this structure, the distance between the N channel region and the P channel region is conventionally 5 to 20 μm.
It can be made much larger, for example, about 100 to 200 .mu.m. Therefore, the latch-up withstand voltage can be greatly improved, contributing to stable operation.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of the configuration of a gate array integrated circuit device using the conventional master slice method, and FIG.
3 is a plan view showing the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention (C), and FIG. g41 is a sectional view of FIG. 3.・N-channel region, IP...P-channel region, 2.. Wiring region, 3.. Input/output terminal and output circuit area, 4.. Base substrate, 5.. Well with conductivity type opposite to that of the base body, 6. ...Well potential setting electrode, 7...N-channel transistor source electrode, 8°°
Gate electrode, 9...Drain electrode of N-channel transistor, 10... Potential setting electrode of base substrate, Source electrode of P-channel transistor, 12...
Gate electrode, 13...
Dry/electrode, 14... Parasitic bipolar NPN transistor, 15... Parasitic bipolar PNN) transistor Representative Patent attorney Noriyuki Chika
(1 other person) Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In a complementary semiconductor integrated circuit device using the master slicing method, in which a chip is made by arranging and integrating a plurality of basic cells on a semiconductor substrate and is provided with wiring patterns as necessary to achieve desired circuit operation, An element row in which P-channel elements are arranged symmetrically with respect to the center line of the element row, and
A complementary method characterized in that element rows in which channel elements are arranged line-symmetrically are arranged alternately across a wiring area, and the element rows on both sides of the wiring area are used to realize a logic function. type semiconductor integrated circuit device.