JPS59165125A - Keyboard interface system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to keyboard interfaces, and more particularly to a serial keyboard inkface system that prevents erroneous transmission of keyboard data due to noise.

[Background technology]

One data line and one clock line are provided between the keyboard and the data processing unit, and the keyboard output code is transmitted serially through the data line, and the keyboard output clock signal is transmitted through the clock line. Keyboard systems have already been proposed. The keyboard output code is the first start bit, followed by an 8 indicating the key position that follows, and a 9 which is the serial scan code of the focus.
Transmitted in bit frames. On the side of the data processing unit, a nine-stage serial-parallel shift register connected to the data line and the clock line is provided, and the bits of the received frame are transferred to the serial-parallel shift register under the control of the clock signal. The bits are sequentially loaded from the lowest M stages of the 9-bit frame, and when the start bit appears at the most significant stage, it is indicated that the reception of the 9-bit frame is complete. The start focus from the top stage of the serial-parallel shift register causes an interrupt request to request the data processing unit to process the scan code in the serial-parallel shift register, and the acquisition process ends. Signals the keyboard that it cannot transmit keyboard data until then.

This keyboard system is very simple as it can send out keyboard data using one data line and one clock line, and the keyboard has its own clock independent of the data processing unit's clock. It has the advantage of being able to work at a pace.

However, in order to improve the economic efficiency of this keyboard system, it was discovered that when a low-cost unshielded stretch cable was used to connect the keyboard and data processing unit, noise caused malfunctions. did. External disturbances typically induce electrostatic discharges into the cable and the noise pulses. noise·
Pulses can occur on both data lines and clock lines. However, the probability that the time point at which the data signal is sampled in response to the transition of the clock signal coincides with the narrow noise pulse is negligible and does not pose any practical problem.

On the other hand, when a noise pulse appears on the clock line, the same data bit is sampled twice: one by the normal clock signal and one by the noise pulse. Therefore, in this case, the 9th pint from the keyboard was actually received in the serial-parallel shift register before the transmission of 9 pints of one frame from the keyboard was completed, and the 9th pint from the keyboard was missing. I will do it.

If the last bit missing is a binary 0 and the data focus sampled twice by the noise pulse is a binary 0 and if the last bit is a binary 1 and the data focus is sampled twice In the case of 1, the number of binary 1s does not change, so the parity check cannot detect this data error.

Data errors caused by such noise pulses can be avoided by using shielded cables, but such cables are very expensive and it is desirable to avoid data errors with unshielded cables. The present invention is intended to solve the problem of erroneous transmissions caused by noise pulses appearing on the clock line.

[Summary of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data processing metrology system in which one data line and one clock line are provided between a keyboard and a data processing unit, and keyboard data is transmitted serially via the data line. An object of the present invention is to provide a serial keyboard interface system capable of solving erroneous transmission of keyboard data due to noise pulses occurring on a clock line.

According to the keyboard interface system of the present invention, it is confirmed between the keyboard and the data processing unit whether the keyboard data has been correctly transmitted 1 to the side of the data processing EI unit. On the data processing unit side, the number of received focuses is counted in response to the clock signal,
When it has counted a number equal to the scheduled number of bits for one frame, it sends a status signal back to the keyboard signaling receipt of the keyboard defocus for one frame. Status signals are sent via data lines.

The keyboard side determines whether a status signal has been returned after the transmission of one frame of data/focus is completed, and receives the status signal before the transmission of one frame of data/focus is completed; A negative acknowledgment signal is transmitted to the processing unit side, and an acknowledgment signal is transmitted when a status signal is received after the transmission is completed. These response signals are transmitted via clock lines. In case of a negative response, the data processing unit discards the previously received data and the keyboard retransmits the same keyboard data. The invention is preferably implemented by a microprocessor.

Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the present invention. A dashed block 6 represents a keyboard, and a dashed block 8 represents a data processing unit. keyboard 6
and data processing unit 8 are connected by one data line 2 and one clock line 4. Key scanning code sending means 1
0 sends a scan output code bit serially to data line 2 in the form of a frame containing the scan code indicating the pressed key. For example, one frame consists of an initial start bit followed by a scan code bit indicating a key position. Clock means 12 sends out one clock pulse for each bit on clock line 4 synchronously with the sending of the serial frame pins. Counting means 14 count the clock pulses sent on clock line 4.

Therefore, the counting means 14 counts the number of serial pinpoints sent out. The counting means 14 generates a transmission count expiration signal TCP to the status determining means 16 when it has counted a number equal to the scheduled number of bits of one frame.

On the other hand, the serial focus and clock pulses sent from the keyboard 6 are given to the receiving section 20 of the data processing unit 8, and the receiving focus counting means 22 of the receiving section 20 responds to each clock pulse on the clock line 4. The number of received focus points is counted, and when a number equal to the expected number of focus points for one frame is counted, a reception count completion signal RCF is generated to the system data sending means 24 through a line 60. Status sending means 24 is responsive to signal RCF on line 60 and applies a status signal to data line 2 via line 62 signaling completion of reception of one frame of serial focus.

The status determining means 16 of the keyboard 1 determines whether a status signal is sent to the data line 2 on the data processing unit side after transmitting all the focus of one frame (71), that is, the counting means 14 also receives a transmission count expiration signal. TCP
(the sword that received the status signal after receiving the status signal). When the status signal arrives after the transmission of one frame is completed, the status determining means 16 generates an affirmative answer signal on the clock line 4 via the line 17.

The keyboard response determination means 26 of the data processing unit examines the clock line 4 via line 33 and determines whether the response from the keyboard is an affirmative response or a negative response.

When the keyboard response determination means 26 detects an affirmative response, it energizes the gate means 28 through a line 64 and transfers the received data/focus to another processing section (not shown) of the data processing unit 8.
to be taken into.

When a noise pulse occurs on the clock line 4 during the transmission period of keyboard data to the keyboard data processing unit 8, the reception focus counting means 22 counts two focus points in one clock period, and counts all the points in one frame. A reception count expiration signal RcFff is generated before the reception of the focus is completed. At this time, the status determining means 16 has not yet received the transmission count expiration signal TCP at the time of receiving the status signal, and therefore supplies a negative acknowledgment signal to the clock line 4 via the line 17, and also sends the key scanning code via the line 18. A control signal is provided to the delivery means 10 and the clock means 12 instructing them to retransmit the same scan code. When the keyboard response determining means 26 detects a negative response, it generates a signal sound on the line 66 to the xD receiving unit 20, discards the received data, and prepares for retransmission.

Next, specific examples of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 shows a specific example in which the keyboard 6 and the data processing unit 8 each use a microprocessor. The keyboard 6 has keys ◆matrix 40, microprocessor v (MPU) 42, open collector
Including gates 44 and 46, data processing unit 8 includes an open collector gate 48, a D-type engine trigger latch 50, a shift 1/disk 52, and a microprocessor (MPU) 541. Data line 2 and clock line 4
are connected to the +5■ power supply via resistors, respectively.

MPU 42 may be, for example, an Intel 8048 microprocessor, and in combination with key matrix 40 constitutes a programmable self-scanning serial keyboard. M.P.
U54 is, for example, Intel's 8086 microprocessor. Open collector game) 44.46.4
8 acts to make the output high when the input is high, and to drop the output to a low level (typically ground) when the input is low.An open collector gate is used, for example, by Texas Instruments. “The TTL Data Book” published by
Second edition, 1976, designated as 5N7407.

MPtJ42U drives the data line through the open collector gate 44 and drives the clock a4 through the open collector gate 46. data line 2
The data line 2 is also connected to the input terminal of the MPU 42 in order to sample the data.

Data line 2 and clock line 4 are connected to shift register 52 . The shift register 52 samples the data signal at the bottom edge of the clock pulse and sequentially shifts it from the lowest stage to the bin iQR of one frame. In this example, one frame consists of a start bit SB at the beginning and an 8-bit scan code N indicative of the subsequent key position. The lowest stage of shift register 52 is connected to the D input of latch 50.

The clock C input of launch 50 is connected to clock line 4.

When the start bit appears at the top of the shift register 52, the launch 50 is set at the falling edge of the clock pulse, causing the ζ output to go high and the ζ output to go low. The low level of the ζ output drives the output of the open collector gate 48 to the -k level (ground), thus making data line 2 all low. Since the data line 2 is clamped to ground level while the latch 50 is set, the keyboard can no longer send out the full data signal.

The high level of the ζ output of latch 50 signals an interrupt request to MPU 54, invoking a program step to perform the necessary processing, such as determining the keyboard response to the status signal. As a keyboard response to the status signal, the MPU 427>- asserts a high level on the clock line 4, and when each signal is returned, the MPU 54 takes in the 8-bit scan code A-Hi of the shift register, and clears the latch 50 and shift register 52. Reset and return to program processing before the interrupt.

When latch 50 is cleared, the ζ output goes to high level,
Open collector gate 48 keeps data line 2 high (+5V). Data line high level state is MPU4
2, which indicates that new frame data can be sent from the keyboard.

When a low level signal is received from the MPU/112 to the clock line 4, the MPU5. ! l is the launch 50 and 7-ft register 5 without taking in the booter of the shift register 52.
Clear 2 and return to program processing before the interrupt.

FIGS. 3A and 3B illustrate operational waveforms for normal keyboard data transmission and erroneous keyboard data transmission, respectively. In Figures 3A and 3B, waveform (a) shows all the clock pulses sent to clock line 4;
b) is the data signal sent to data line 2, waveform (C)
is the ζ output power of the latch 50) and the signal given to the data acid via the open collector gate 4B, waveform (d)
is the MPU42 power; the sample that samples data line 2;
The timing waveform (e) shows the sample timing when the MPU 5d samples the clock line 4 after the interrupt.

In FIG. 5A, when the MPU 54 is ready to accept keyboard data, the MPU 54 latches the latch 50.
is cleared, or set to a high level as shown at 61 in waveform (C).

MPU 42 samples data line 2 to see if it is at a high level (step 78 of the program flowchart of FIG. 4). After confirming that the data line 2 is at a high level, data transmission operation begins.

MPU42 is (first start bit SB) plus (
The subsequent 8-bit scan code) sends all the frame bits serially to data line 2. The preferred high level period and low level period of clock pulse (a) are 50 μS to 100 μs and 25 μS to 50 μs, respectively.
However, in this example, each time is set to 50 μS. However, one shift of the high level period and the low level period is not important.

Data signal (b) //i is sampled and captured in shift register 52 on the falling edge of clock pulse (a). Therefore, the data signal jt (b) is at least black,
It is necessary to have a significant data level at the falling edge of pulse (a). In this example, each bit has 2.5 digits before the rising edge and 2.5 digits after the falling edge of the clock pulse.
When sampling on the falling edge, it is important to have a significant data level on the falling edge of the clock pulse.

Furthermore, in order to detect the status signal from the data processing unit, the MPU 12 needs to set the data line to a high level at least at the data line sample time.

If MPU 42 were to drive data@2 to a low level (ground level) at the sample time, data line 2 would be flagged and the state of the Q output of latch 50 would not be detected correctly. Therefore, the MPU is 6 in waveform (b).
As shown in Figure 0, regardless of whether the bit to be transmitted is II 1 $1 or “0#,” data @2 is set high for a predetermined period in the second half of the clock period, and during this high level period, MPU 42 samples data line 2, which is 2.5μ from the falling edge of each clock pulse.
s It is set to the elapsed level of Ryodaka.

Note that in the figure, the data signal (b) and the Q output (e) of the latch 50 are shown separately for convenience, but a high-level logical AND of the waveform (b) and waveform (C) appears in data @2. .

Therefore, in the program step, when the MPU 42 confirms that all the data lines are at high level in step 78 of FIG.
B)'fr:F:n In addition, step 80L2. of FIG.
After 5 μs, set the clock line 4 to high level for a period of 8 seconds.
2) Set the clock line A k to low level step 84
), 2.5 μs later, data line 2 is brought high (step 86). MPU 42 samples data @2 every clock cycle (step 88) and checks to see if a status signal has been sent from the data processing unit (step 90). If no status signal is detected, the process returns to step 80 and the bit transmission operation is repeated.

When the 9 bits of one frame are loaded into the shift register 52 and the start bit SB is shifted/appears at the top of the raster 52, the clock signal of clock cycle 9 is
At the falling edge of the pulse, the launch 50 is sent out and the Q output goes low, sending out a low level status signal to the data line 2 (62 in waveform (c)). Since the receive bit counting operation and the status signal sending operation are performed in hardware by the shift register 52 and the launch 50, respectively, these operations are performed by the broken line block 1 in FIG.
02 and 106 are shown separately.

MPtJ12 detects the status signal at sample 9 of clock cycle 9. In this case, since the MPU 42 detects all the status signals after the transmission count is -9 and the transmission of one frame is completed, this indicates correct transmission, and the MPU 12 receives the clock signal as shown in waveform (a) 64.
Following cycle 9, clock line 4't- is brought high (step 94 in FIG. 4).

This represents an acknowledgment.

When the latch 50 is set, the Q output requests an interrupt to the MP[J54 (step 104 in FIG. 4), and the MPU5
．． In response to this, the keyboard response 41 to the status signal is output by pulsing the clock line 4 at a predetermined time period from the interrupt as shown in the waveform (,) (step 108 in FIG. 4) and determining whether the level is high. A determination is made (step 110). In this case, a high level is detected and the MPU
54 is the scanning code A-H? of the shift register 52. After L is taken in (step 112), the latch 50 and shift register 52 are cleared (step 114), and the Q output is set to a high level, and the keyboard is notified that the keyboard data can be sent. Return operation returns to the program before the interrupt (Step 1
16).

FIG. 3B illustrates the case where a noise pulse 66 appears on clock pulse (a) during clock cycle 5. Noise pulses due to electrostatic discharge can occur in both positive and negative polarities, but since clock line 4 is clamped to ground level during the clock low period, positive noise pulses during the clock low period are absorbed and are effectively ignored. It doesn't cause any problems. The problem is the negative noise pulse during the clock high period.

In this case, the shift register 52 has two shifts in one clock period.
Sample the data twice on each falling edge. Therefore, the start bit SB [appears at the top of shift register 52 in clock cycle 8 and returns a low level status signal to the keyboard in clock cycle 8 (waveform (
c) 70). This status signal is sampled by MPU 42 on clock cycle 8. At this time, the transmission count is N9 and the transmission is not completed, so MP
, U42 drives clock line 2 low following clock cycle 8 (step 98 in FIG. 4) as shown at 68 in waveform (a), which represents a no answer. A sufficient time after the interrupt, MPU 54 samples clock line 4 to detect this low level. MPU54 is shift register 5
Clear the latte 50 and shift register 52 without taking in the data of step 2 (step 118), and return to the program processing before the ful1 interrupt in the return step (step 118).
Step 12n) continues another process until interrupted again by a retransmission. The MPU 42 prepares for retransmission (step 100), and after confirming the data line high level in step 78, retransmits the same scan code.

The duration of the noise pulse due to electrostatic discharge is 1O-10
It should be about 0 ns, and according to experience it should be at least 10 ns.
Occurs at intervals of m5 or more. This interval plus (1 frame transmission time) plus (status detection/response/retransmission)
The time required for this is quite long, and it is almost impossible for an erroneous transmission to be detected again due to retransmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a diagram showing an implementation sequence of the present invention, and FIGS. 6A and 3B illustrate operations in the case of normal transmission and in the case of erroneous transmission, respectively. The waveform diagram and FIG. 4 are program flowcharts in the implementation of FIG. 2. Applicant Internanta Nano L/-Hisaku Machines
Figure 1 Figure 3A

Claims (1)

[Claims] A keyboard and a data processing unit,
A keyboard interface system for a data processing device connected via a clock line transmitting a clock signal and a data line transmitting serially in synchronization with said clock signal, a serial frame viratra containing a key scanning code representing a key. and, provided in association with the data processing unit, a counting means for counting the number of received bits in response to the clock signal; means for applying a status signal to the data line indicative of receipt of a frame of bits in response to counting a number equal to a predetermined number of bits;
means for applying a negative acknowledgment signal to the clock line when the status signal is received before one frame of keys is completed; and means associated with the keyboard and responsive to the negative acknowledgment signal; and means for retransmitting key scan codes of the same frame.