JPS59164093U - Waveform data generator - Google Patents

Waveform data generator

Info

Publication number
JPS59164093U
JPS59164093U JP5675383U JP5675383U JPS59164093U JP S59164093 U JPS59164093 U JP S59164093U JP 5675383 U JP5675383 U JP 5675383U JP 5675383 U JP5675383 U JP 5675383U JP S59164093 U JPS59164093 U JP S59164093U
Authority
JP
Japan
Prior art keywords
data
waveform
count value
cycle
storage circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5675383U
Other languages
Japanese (ja)
Other versions
JPS6336399Y2 (en
Inventor
山田 恒雄
茂 沖田
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP5675383U priority Critical patent/JPS59164093U/en
Publication of JPS59164093U publication Critical patent/JPS59164093U/en
Application granted granted Critical
Publication of JPS6336399Y2 publication Critical patent/JPS6336399Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の構成を示すブロック図。第
2図は本考案の一実施例の作用の説明に供する模式図。 1・・・ROM、2・・・クロックパルス発振器、3゜
4および5・・・分周器、6,8および13・・・マル
チプレクサ、9・・・減算器、10・・・除算器、11
・・・アドレス判別回路、12・・・データ設定器、1
4・・・加算器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram for explaining the operation of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... ROM, 2... Clock pulse oscillator, 3°4 and 5... Frequency divider, 6, 8 and 13... Multiplexer, 9... Subtractor, 10... Divider, 11
... Address discrimination circuit, 12 ... Data setter, 1
4... Adder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 壱周期間の正弦波形を所定間隔でサンプリングした値を
符号化し波形データとして記憶させた記憶回路と、クロ
ックパルスを計数する計数手段と、該計数手段の計数値
データaをアドレス指定データとしたとき計数値データ
が0≦a≦旧周期内にあるか一周期< a ’−−周期
内にあるかを判別するアドレス判別回路と、前記計数手
段の計数値データから前記M周期時における前記計数手
段の計数値データを減算する減算手段と、該減算手段の
出力データを除数2で除算する除算器と、前記アドレス
判別回路の出力に対応して前記計数手段の計数値データ
と前記除算器の出力データとの何れか一方を選択して前
記記憶回路ヘアドレス指定データとして供給する第1の
選択手段と、前記アドレス判別回路の出力に対応し、て
前記第1の選択手段による前記計数値データの選択中前
記記憶回路から読み出された波形データを選択出力しか
つ前記第1の選択手段による前記除算器の出力データ選
択中前記正弦波形の振幅値を符号化したデータと前記−
周期時における波形データとの差データに前記記憶回路
から読み出された波形データを加えたデータを選択出力
する第2の選択手段とを備えてなることを特徴とする波
形データ発生装置。
A storage circuit that encodes the values obtained by sampling a sine waveform for one cycle at predetermined intervals and stores it as waveform data, a counting means for counting clock pulses, and when count value data a of the counting means is used as addressing data. an address discrimination circuit that determines whether the count value data is within 0≦a≦old cycle or within one cycle<a'--cycle; and the counting means at the time of the M cycles based on the count value data of the counting means. a subtracting means for subtracting the count value data of the subtracting means, a divider for dividing the output data of the subtracting means by a divisor 2, and a count value data of the counting means and an output of the divider corresponding to the output of the address discrimination circuit. a first selection means which selects one of the data and supplies the data as address designation data to the storage circuit; During selection, the waveform data read from the storage circuit is selected and outputted, and while the output data of the divider is selected by the first selection means, the data obtained by encoding the amplitude value of the sine waveform and the -
A waveform data generation device comprising: second selection means for selectively outputting data obtained by adding the waveform data read from the storage circuit to the difference data from the waveform data at the time of the period.
JP5675383U 1983-04-18 1983-04-18 Waveform data generator Granted JPS59164093U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5675383U JPS59164093U (en) 1983-04-18 1983-04-18 Waveform data generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5675383U JPS59164093U (en) 1983-04-18 1983-04-18 Waveform data generator

Publications (2)

Publication Number Publication Date
JPS59164093U true JPS59164093U (en) 1984-11-02
JPS6336399Y2 JPS6336399Y2 (en) 1988-09-27

Family

ID=30187073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5675383U Granted JPS59164093U (en) 1983-04-18 1983-04-18 Waveform data generator

Country Status (1)

Country Link
JP (1) JPS59164093U (en)

Also Published As

Publication number Publication date
JPS6336399Y2 (en) 1988-09-27

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