JPS5916369A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the collector series resistance as well as to enhance the high-speed performance of the titled device by a method wherein a transistor, for which high-speed performance is required, is formed at the part where impurities will be selectively diffused simultaneously with the diffusion to be performed for formation of a high density semiconductor region for connection of a collector electrode. CONSTITUTION:Donor impurities are selectively diffused on the surface of a P type Si semiconductor substrate 1, an N type buried layer 2 is formed, then acceptor is selectively diffused on the surface of said semiconductor substrate 1, and P<+> type region 4 is formed. Subsequently, an N<+> type region, having the density higher than that of the N<+> type buried layer is formed by selectively diffusing donor impurities again in such a manner that said N<+> type region is partially overlapped on the N<+> type buried layer 2, and an N<-> type semiconductor layer 6 is formed on the semiconductor substrate 1. Then, a P<+> type region 4a is formed by selectively diffusing acceptor on the part corresponding to the P<+> type region 4 located on the surface of said N<+> type semiconductor layer 6. Subsequently, after donor impurities have been doped on the part corresponding to the N<+> type regions 2 and 5 located on the surface of the semiconductor layer 6, donor impurities are diffused. Lastly, a transistor element is formed by performing a diffusing process for formation of a base region an another diffusion process is performed for formation of an emitter region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device.

For example, in acoustic semiconductor integrated circuit devices, it is important to form a power transistor that requires a high breakdown voltage and a transistor that does not necessarily require a high breakdown voltage but requires high speed on the same semiconductor substrate. This became necessary for miniaturization.

According to the conventional method of simultaneously forming both transistors with different requirements on one substrate, the impurity concentration of the epitaxial growth layer in which the transistors are formed can be kept above a certain level in order to ensure the breakdown voltage of the power transistor. Therefore, it was not possible to sufficiently increase the speed of the other transistor.

Therefore, after forming an epitaxial growth layer, a method of selectively diffusing impurities into the part where a transistor that requires high speed is to be formed may be considered to reduce the series resistance of the collector (and thereby ensure high speed). .

However, the above method requires a new series of steps for partial diffusion.

The main purpose of the present invention is to improve the high-speed performance of 10,000 transistors in an IC without increasing the number of steps, and a secondary purpose is to reduce the leakage current of parasitic transistors formed in the operating area of such transistors. .

The basic structure of the present invention for achieving the above object is as follows:
selectively forming first and second semiconductor regions of a second conductivity type at a distance from each other on the entire surface of a first semiconductor layer of a conductivity type; a step of forming a second semiconductor layer of a second conductivity type on the whole surface of the semiconductor layer; a step of forming a third semiconductor region extending between the second semiconductor region and the main surface of the second semiconductor layer; and forming first and second transistor elements in a second semiconductor layer and a third semiconductor region on the first semiconductor region, respectively.

The present invention will be explained below with reference to Examples.

The drawings show an embodiment of the present invention in the order of steps.

An N-type buried layer 2 is formed by selectively diffusing a donor such as phosphorus onto the surface of a P-type Si semiconductor substrate 1 (see FIG. 1). Next, by selectively diffusing an acceptor such as boron into the surface of the semiconductor substrate 1, a P+ type region 4 for junction isolation is formed (FIG. 2). Thereafter, a donor is selectively diffused over a portion of the N++ buried layer 2 on the surface of the substrate 1 to form an N+ type region having a higher concentration than the N++ buried layer (FIG. 3). Next, an N-type semiconductor layer 6 is formed on the semiconductor substrate 1 by an epitaxial growth method (FIG. 4).
. Then, an acceptor is selectively diffused into a portion of the surface of the semiconductor layer 60 corresponding to the P1 type region 4 for junction isolation described above to form a P+ type region 4a (FIG. 5). Next, portions of the surface of the semiconductor layer 60 corresponding to the N+ type regions 2 and 5 are doped with donors by ion implantation (FIG. 6). The implanted donor is then subjected to a diffusion treatment.

Through the above processing, the semiconductor becomes shaped as shown in FIG. Finally, a transistor element is formed by performing diffusion to form a base region and diffusion to form an emitter region (FIG. 8).

According to the present invention as described above, a transistor that requires high speed is formed in a portion where impurities are selectively diffused at the same time as the diffusion to form a high concentration semiconductor region for collector electrode connection. The impurity concentration of the collector can be made higher than the impurity concentration of the collectors of other transistors formed at the same time. Therefore, for transistors that require high speed performance, the collector series resistance can be lowered, and therefore the high speed performance can be increased.

On the other hand, with this method, each region of the transistor that requires a high breakdown voltage is not affected in any way, and the breakdown voltage can be ensured. Furthermore, since the diffusion process to increase the impurity concentration is performed at the same time as the diffusion process to form the high concentration semiconductor region for connecting the collector electrode, the number of manufacturing steps is not increased.

Note that if it is necessary to further increase the impurity concentration of the highly doped semiconductor region for connecting the collector electrode in order to extremely reduce the collector resistance of a transistor that requires a high breakdown voltage, the sixth embodiment of the above embodiment In addition to the ion implantation step shown in the figure, a step of selectively adding impurities to the highly doped semiconductor region for collector electrode connection is added.

The present invention can be widely applied to methods for manufacturing semiconductor integrated circuit devices having two or more transistor elements having mutually different characteristics.

[Brief explanation of drawings]

The drawings (FIGS. 1 to 8) show an embodiment of the present invention in the order of steps. 1... P-type semiconductor substrate, 2... N-type buried layer, 3...
・5in2 membrane, 4... P wall area for junction separation, 5...
Diffusion region for forming a high concentration region for collector electrode connection, 6... Semiconductor layer, 7... High concentration region for collector electrode connection, 8... Base region, 9... Emitter region, 10. ...Electrode, A...Transistor element section requiring high breakdown voltage, B...Transistor element section requiring high speed performance. ,・−゛、

Claims (1)

[Claims] 1. selectively forming first and second semiconductor regions of a second conductivity type separated from each other on one main surface of a first semiconductor layer of a first conductivity type; the first and second semiconductor regions; a third semiconductor layer extending between the second semiconductor region and the main surface of the second semiconductor layer; A semiconductor integrated circuit device comprising the steps of forming a region, and forming first and second transistor elements in a second semiconductor layer and a third semiconductor region on the first semiconductor region, respectively. manufacturing method.