JPS59163622A - Identification system for various function blocks constituting information processing system - Google Patents

Abstract

PURPOSE:To eliminate the use of an exclusive line for identification signal by transmitting the data signal and the synchronizing signal at the transmission side after superposing both signals on each other through an exclusive OR circuit and separating the data signal at the reception side through said OR circuit and with use of an existing synchronizing signal. CONSTITUTION:A synchronizing signal X for identification signal is produced for function blocks A (upper) and B (lower) from the clock and frame signals via dividing counters DCa and DCb and then applied to an input side of exclusive OR circuits ELOa and ELOb respectively. The data signal lines DL and DA are added to the other input side of the circuits ELOa and ELOb respectively. The signal sent to the block A via the line DL is equal to an exclusive OR signal of signals DA and X, and this signal restores the signal DA at the output side in the circuit ELOa by the signal X sent from the counter DCa. The signal DA is supplied to a function circuit Fa. While a coincidence circuit CC to which the signals DA and X are applied keeps an immobile state since no coincidence is obtained between both signals.

Description

DETAILED DESCRIPTION OF THE INVENTION ta) Technical Field of the Invention The present invention relates to an improvement in a system for identifying the presence or absence of various functional blocks constituting an information processing system, and particularly to an identification system that eliminates the need for dedicated signal lines.

fb) Background of the technology So-called information processing systems, such as electronic exchange systems or computer systems, are configured in so-called hardware with a large number of functional blocks of various sizes, and are processed in so-called software by programming to perform desired processing tasks. As is well known.

At this time, the number of functional blocks of various sizes configured in hardware differs depending on the scale of processing even in the same functional system configuration, but in such cases, the complexity of programming due to performing processing in software can be reduced. In order to avoid this problem, measures are generally taken to have a higher-level functional block identify the presence or absence of a lower-level functional block between functional blocks.

(C) Prior art and problems The most widely used method in the past as a means for identifying the presence or absence of the above-mentioned 10th functional block in a higher-order functional block is to detect the presence of the block by detecting the presence of a specific potential, such as the earth's potential. This potential is recognized by the upper functional block via a dedicated line.

FIG. 1 shows an example of the above-mentioned known system in the form of a block diagram. The upper functional block A and the lower functional block B are connected to the respective functional circuits Fa and Fb or the data signal line DL.
, a clock signal line CL, and a frame signal line FL, as shown schematically in the second part of each line.The lock signal and frame signal perform normal functional operations in an orderly manner, and data signals are transmitted and received. be done. Of course, this operation function is only available when function block B exists, and if it does not exist, the above operation function is performed on another block 3 with the same function (not shown), or an action that cannot be performed at all is performed on the upper level. A dedicated identification signal line EL is provided to identify the functional block A, and in the illustrated example, the ground potential on the block B side is transmitted to the functional block A as an identification signal of its presence. The gate circuit G provided on the block A side has an earth potential on the input side (block B
(existence of block B) or voltage V exists (absence of block B)
For example, a 1 signal or a 0 signal is sent to the functional circuit Fa depending on the purpose.

Although the above-mentioned conventional system has a simple structure, it has the disadvantage that a dedicated identification signal line EL must be provided for each individual functional block, which naturally increases in number as the scale of the system increases.

Furthermore, if the power supplies for both functional blocks A and B must be provided separately and independently, for example, block A
If block B is composed of SI logic circuits and non-logic circuits including electromagnetic relays, etc., the dedicated identification signal line EL as well as other signal lines D'L and C may be used.
L and FL must also be connected to blocks A and AB, for example, by using transformer coupling, so the identification method shown in FIG. 1 cannot be used as is.

(d1 Purpose of the Invention) The present invention eliminates the drawbacks of the conventional method described above, eliminates the need for a dedicated identification signal line, and provides a novel system of this type that can be used even between functional blocks that must each have separate and independent power supplies. The purpose is to obtain an identification method.

(e1 Structure of the Invention The object of the present invention is to provide a means for creating an identification synchronization signal, and in the transmitting side functional block, the signal and the above are connected via a signal line originally connected for another purpose. The synchronization signal is superimposed using an exclusive OR circuit and sent out, and in the receiving side functional block, the exclusive OR circuit is used again to
This is achieved by the identification scheme according to the invention, which is arranged to use a pre-existing synchronization signal to separate the signals of one originally intended for another purpose.

The synchronization signal for the identification signal can be easily created using a frequency division counter from the clock signal and frame signal that exist in any functional block. In addition to the above-mentioned signal lines necessary for control order, at least one data signal line is connected between the functional blocks, so in the present invention, this signal line is used for sending out the synchronization signal for the identification signal together with the data signal. be done.

The identification synchronization signal created by the upper functional block that receives this is used to separate the incoming data signal by an exclusive OR circuit when the lower functional block exists, and when the lower functional block does not exist, it is used as it is from the circuit. Differences between the two can be identified by outputting them.

Unlike conventional methods, this method does not rely on identifying the presence or absence of a specific potential, so the power supplies for both upper and lower functional blocks must be used independently of each other, and all connection lines are connected via transformers. You can use it as is even when you are using it.

+f1 Embodiments of the Invention The gist of the present invention will be specifically explained below with reference to the embodiments shown in FIG. The same reference numerals as in FIG. 1 indicate the same objects.

In functional blocks A (upper) and B (lower), an identification signal synchronization signal X is created from the clock signal and the frame signal via frequency division counters DCa and DCb, and one of the exclusive OR circuits ELOa and ELOb is generated, respectively. is attached to the input side. A data data signal line DL and a data signal DA to be sent are provided to the other input sides of the exclusive OR circuits ELOa and ELOb, respectively, and therefore the signal sent to the functional block A via the data signal line DL is as follows. This is an exclusive OR signal of the data signal DA and the synchronization signal
The data signal DA is sent to the output side by the synchronization signal X from Ca.
is restored and assigned to the functional circuit Fa. In addition, when the signal DA and the synchronization signal X are applied and the functional block B does not exist, there is no input from the signal line DL of the exclusive OR circuit ELOa, and therefore its output is the synchronization signal X itself from the frequency division count DCa. Therefore, the coincidence circuit CC operates to cause the functional circuit Fa to identify the absence of the functional block B.

(As described in the detailed explanation of g1 invention, the method of the present invention does not require a dedicated line for the identification signal, and uses a synchronization signal instead of the identification signal of a specific potential, thereby making the Denkai system different. It has an industrial effect that can be used even in various cases.

[Brief explanation of drawings]

FIG. 1 shows a conventionally widely used identification method, and FIG. 2 shows an embodiment of the identification method according to the present invention, both in block diagram form. In the figure, A and B are separate functional blocks, Fa. Fb is the functional circuit of each functional block, DL, CL, F
L is a data signal line, a clock signal line, a frame signal line, and ELOa that connect both blocks. ELOb is an exclusive OR concave path, DCa and DCb are frequency division counters, and CC is a coincidence circuit.

Claims (1)

[Claims] Both C11 and C11 include means for creating a synchronization signal for identification signal,
In the transmitting side functional block, this signal and the above-mentioned 101 signal are superimposed using an exclusive OR circuit and sent out via a signal line originally connected for another purpose, and the receiving side functional block , a method for identifying the presence or absence of various functional blocks constituting an information processing system, characterized in that the exclusive OR circuit is used to separate signals originally intended for different purposes using a pre-existing synchronization signal. (2) Presence or absence of various functional blocks constituting the information processing system according to claim 1, wherein the identification signal synchronization signal is created from a clock signal and a frame signal via a frequency division counter. Identification method.