JPH0284846A - Status signal transfer system - Google Patents

Abstract

PURPOSE:To transfer only a status signal with a few amount of change via a V.11 interface (universal balanced double-current mutual connection circuit) including a transformer by providing a consecutive pulse generating means, an encoding means, and a decoding means. CONSTITUTION:An OR circuit 80b in an encoding part 80a takes the OR of the status signal 20 and a consecutive pulse 10 of prescribed cycle from a consecutive pulse generation circuit 70a, and converts the signal 20 to a form representing the presence/absence of the pulse 10, and outputs it from the V.11 interface circuit 2. Next, the signal is inputted to the V.11 interface circuit 4 in a decoding part 90a via the transformers T1 and T2, and the leading edge or the trailing edge of the pulse 10 is detected by a signal conversion part 90b, and it is decoded to the status signal 6 of L or H. In such a way, it is possible to transfer only the signal 20 with a few amount of change via the circuits 2 and 4 including the transformers T1 and T2, and to increase the number of bits to be transferred arbitrarily.

Description

[Detailed Description of the Invention] [Summary] Regarding a status signal transfer method that transfers a status signal that does not change much through an interface circuit that includes a transformer, the present invention relates to a status signal transfer method that transfers a status signal that does not change much through an interface circuit that includes a transformer. The purpose is to provide a status signal transfer method that can transfer signals other than status signals, such as @L11 or "H" changes, which are directly extracted and transferred through the transmitting transformer.
The status signal L'' or H'' is converted into the presence or absence of continuous pulses generated by the continuous pulse generating means through the encoding means, transferred through the transmitting transformer, and is detected by the receiving transformer as the rising or rising edge of the continuous pulse. The falling edge is detected by the decoding means, and this is set to “L” or “H”.
and configured to decode the status signal of the state.

[Industrial application field]

The present invention relates to a status signal transfer method for transferring status signals with little change via an interface circuit having a transformer.

Usually, status signals are Cronk, Data.

It is a general term for signals other than data processing timing signals, and is used to set the functions of devices in a communication system.

Incidentally, if the functional settings of the devices making up the communication system change while signals are being exchanged via the communication system, this will lead to data abnormalities.

Further, the alarm signal displayed as a status signal indicates various abnormalities in the communication system, and the alarm signal causes the communication system to perform operations such as stopping data exchange or retrying data exchange.

In communication systems, for example, by performing processing on alarm signals such that if the data transfer is normal, the state remains normal, and if it is abnormal, the abnormal state persists for some time, this reduces the number of operation switches in the event of an abnormality and ensures smooth data processing. That's what I do.

Therefore, the status signal generally does not change much. However, if such a status signal that changes little is to be transferred via a V,11 interface including a transformer, it is virtually impossible to transfer it.

Therefore, the practical implementation of a method for transferring such signals using a simple method is awaited.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart in the conventional example.

In this example, a signal is transferred via a V,11 interface including transformers T1, T2, and the V,11 interface is a general-purpose balanced These are the electrical characteristics recommended by CCITT for double-current interconnection circuits.

■, 11 interface has a data signal speed of 1OMbp
It specifies the electrical characteristics of integrated balanced interconnection circuits used in data terminal equipment and data line termination equipment below s.

That is, it shows indicators for the output impedance, output power, waveform of the signal generator, sensitivity and balance of the receiver, and compatibility with other interfaces.

Cables and terminations, multipoint operation, etc. are also noted.

An example of data communication using this V,11 interface is shown in FIG.

That is, code 1 on the transmitting side is a time division multiplex conversion device, and the frame pattern F, data D, and status signal O input to the time division multiplex conversion device 1 are converted into a timing signal TIMI.
, 2 and time-division multiplexing into one frame format ■■.

11 is sent to the line (al) via the interface circuit 2.

In addition, ■, a transformer Tl is installed between the 11 interface circuit 2 and the line (81) for impedance matching when the line (a) is long distance and for preventing DC noise from being mixed into the signal. .

On the other hand, code 4 on the receiving side is v, 11 interface on the sending side.
V provided corresponding to the circuit 2.

11 interface circuit 4, and similarly to the transmitting side, a transformer T2 is provided between the lines (al and 2) and the 11 interface circuit 4.

(2) The data received via the 11 interface circuit 4 is taken into a frame pattern detection circuit 5 and sent to the status signal extraction circuit 6.

When the frame pattern detection circuit 5 detects a frame pattern in the data, the detection pulse causes the status signal extraction circuit 6 to extract the status signal 0 from the data at the timing of the clock CLK and send it to the next stage.

Note that the time division multiplex conversion device 1. V, 11 interface circuits 2 and 4. The status signal extraction circuit 6 is also integrated into an integrated circuit.

The above-mentioned functional blocks are for transferring status signals [phases], and are processed according to a time chart as shown in FIG. In addition, the frame format of the transfer signal■
In other words, when a signal is transferred via the V, 11 interface circuits 2 and 4 including transformers T1 and T2, the voltage induced in transformers TI and T2 is A transformer T1. in which the electromotive force or potential generated by the change in magnetic field is generated by a change in the magnetic field. Transfer due to the properties of the coil inside T2.

Therefore, the frame pattern F has relatively many signal changes.
The status signal [phase] with little change in data D and
As shown in the figure, the timing signal TIM1.2 is inserted by the time division multiplex converter 1 and transferred.

V, 11 interface circuit 4 that performs a signal receiving function
The frame pattern detection circuit 5 detects a frame pattern from the received continuous data, creates a timing signal TIM3 for extracting status signal 0, and uses this timing signal TIM3 to detect a frame pattern in the status signal extraction circuit 6.
extracts the status signal ◎ from continuous data.

[Problem to be solved by the invention]

Usually, the frame format of the signal to be transferred is determined in advance in accordance with the communication system, as shown in FIG. Therefore, if the number of bits of the status signal [phase] is increased, data D etc. other than the status signal [phase] will be reduced.

This means that when transferring data D whose number of bits is determined in advance, the number of bits of the status signal [phase] cannot be increased.

Further, there is a problem that the status signal 0 cannot be transferred unless a changing signal such as data D is being transferred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a status signal transfer method that can transfer only status signals that change little through a V,11 interface that includes a transformer.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 70 is continuous pulse generating means for generating continuous pulses of a predetermined period, and 80 is a clock, data, data processing timing signal [
A general term for signals other than [Phase], which refers to the settings of devices that make up a communication system, the configuration status of the devices, and transmission paths.

It is an encoding means that converts the status signal [phase] indicating the state of data into the presence or absence of continuous pulses, and 90 detects the rising or falling edge of the received continuous pulses, and detects the "L" or "H" state. This is a decoding means for decoding into a status signal (■), and by providing such means, it is a means for solving this problem.

(Function) The encoding means 80 outputs "L" or "L" of the status signal [phase].
Converting "H" into the presence or absence of a continuous pulse of a predetermined period generated from the continuous pulse generating means 70, and processing this continuous pulse so that it is decoded by the decoding means 90 into a status signal of "L" or "H". Therefore, it is possible to transfer only the status signal [phase] with little change through the v, 11 interface including transformers T1 and T2, so the number of bits of the status signal [phase] to be transferred can be increased arbitrarily. It becomes possible.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart in an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses the continuous pulse generating means 70 described in FIG. Continuous pulse with a specified period [phase]
and (1) an OR circuit (hereinafter referred to as an OR circuit) 80b that calculates the logical OR of the status signal [phase] and converts the status signal [phase] into the presence or absence of a continuous pulse [phase].

11 an encoding unit 80a consisting of an interface circuit 2;

The decoding means 90 includes a signal conversion section 90b that detects the rising or falling edge of the continuous pulse [phase] converted by the encoding section 80a and converts it into a status signal of "L" or H; This is an example configured from a decoding section 90a made up of an interface circuit 4.

The status signal ■ is inputted to one side of the OR circuit 80b in the encoding unit 80a, and the continuous pulse 0 of a predetermined period generated from the continuous pulse generation circuit 70a based on the clock CLK generated from an oscillator (not shown) is inputted to the other side. , the “L” or H state of the status signal [phase] is continuously pulsed [phase]
, and is sent to line (a) via transformer T1.

The conversion situation at this time is shown in FIG. In other words, ■ in Fig. 3 indicates that the "L" state of the status signal [phase] is a continuous pulse [phase].
The "H" state is converted to a state with no continuous pulse 0.

This continuous pulse [phase] is taken out from transformer T2,
The decoding section 90a detects the rising or falling edge of this continuous pulse [phase], and decodes it into a status signal (2) in the "L" or "H" state based on this detected pulse (2) as shown in FIG.

In the example shown in FIG. 3, the signal is decoded into an "L" state status signal upon detection of a falling edge.

In addition, the change from "L" to "H" state is a continuous pulse [phase]
In order to distinguish the period of the detection pulse ■ from the resistor R,
Multiplying the CR time constant circuit consisting of capacitor C, if the state of no continuous pulse [shares] continues for more than the CR time constant.
It is assumed that the status signal is in the H” state.

The time constant of the CR time constant circuit of this embodiment is such that when there is a continuous pulse [phase], the "L" state continues, and when the state without continuous pulses equal to or greater than the time constant continues, the CR time constant circuit changes from the "L" state to the "H" state.
” state, but if the time constant is extremely long from the period of the continuous pulse (as shown in the bottom row of Figure 3), the state changes to “L”.
Since there is a delay in changing from the "H" state to the "H" state, the time constant is set to be slightly larger than the period of the continuous pulse [phase] (as shown in the upper part of the square in FIG. 3).

As described above, since only the status signal can be transferred, the number of bits of the status signal can be arbitrarily set.

〔Effect of the invention〕

According to the present invention as described above, V, 11 including a transformer
Only status signals that change little can be transferred through the interface.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. FIG. 5 is a block diagram explaining an example, and FIG. 5 is a diagram explaining a time chart in a conventional example. In the figure, 1 is a time division multiplex conversion device, 2.4 is V, 11 is an interface circuit, 5 is a frame pattern detection circuit, 6 is a status signal extraction circuit, 80 is an encoding means, 80b is an OR circuit, 90a are the decoding part and , respectively. 80a is an encoding unit; 90 is a decoding unit; 90b is a signal converting unit; FIG. 1 is a block diagram illustrating the present invention in detail;

Claims (1)

[Claims] A digital status signal ([20]) that continuously changes to "L" or "H" is extracted and exchanged through transformers (T1, T2) provided on the transmitting side and the receiving side, respectively. It is a status signal transfer method that uses continuous pulse generation means (
70), and the status signal ([20]), which is a general term for signals other than clocks, data, and data processing timing signals, and indicates the settings of devices constituting a communication system, the configuration status of the devices, transmission paths, and data status. encoding means (80) for converting into the presence or absence of the continuous pulse; detecting the rising or falling edge of the received continuous pulse;
A decoding means (90) is provided to decode the status signal ([6]) in the "H" state, and a change in "L" or "H" of a signal other than the status signal ([20]) is directly transmitted. "L" or "H" of the status signal ([20]) is determined by the encoding means (80) depending on the presence or absence of the continuous pulse generated from the continuous pulse generating means (70).
) and transferred through the transmitting transformer (T1), and the rising or falling edge of the continuous pulse extracted by the receiving transformer (T2) is converted into the decoding means (9).
0) and decodes it into the status signal ([6]) in the "L" or "H" state.