JPS5916340A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5916340A JPS5916340A JP12641482A JP12641482A JPS5916340A JP S5916340 A JPS5916340 A JP S5916340A JP 12641482 A JP12641482 A JP 12641482A JP 12641482 A JP12641482 A JP 12641482A JP S5916340 A JPS5916340 A JP S5916340A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- substrate
- resist
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] The present invention relates to a method of manufacturing a semiconductor device.
半導体集積回路技術の最近の進歩により、トランジスタ
のサイズは線幅2〜3μmのものかあられれ、2μm以
下のものも研究段階では可能となってきた。しかし、ト
ランジスタサイズが小さくなっても、分離領域が小さく
ならなければ集積回路(以降LSIと呼ぶ)の高密度化
は実現できない。まだ現在用いられている選択酸化法で
はバーズ・ピークと呼ばれる酸化膜の活性領域への張り
出しがあり、トランジスタの幅(W)が設計より小さく
なり、微細化の防げになるばがりが、MO3LSIでは
一種の狭チャンネル効果を引き起こしたり、伝達コンダ
クタンスを低下させる。現状のトランジスタサイズ20
〜30μmではまだ選択酸化で素子分離は対応できるが
、10〜20μm以下となると、その対応はバーズビー
クのため困難となる。Due to recent advances in semiconductor integrated circuit technology, the size of transistors has ranged from 2 to 3 .mu.m in line width, and it has become possible at the research stage to have line widths of 2 .mu.m or less. However, even if the transistor size becomes smaller, unless the isolation region becomes smaller, high density integrated circuits (hereinafter referred to as LSIs) cannot be realized. In the currently used selective oxidation method, there is a protrusion of the oxide film into the active region called a bird's peak, which makes the width (W) of the transistor smaller than the design and prevents miniaturization, but in MO3LSI, It causes a kind of narrow channel effect or reduces the transfer conductance. Current transistor size 20
For a thickness of ~30 μm, element isolation can still be achieved by selective oxidation, but for a thickness of 10 to 20 μm or less, this becomes difficult due to bird's beaks.
本発明は上記欠点にかんがみなされたもので、微細化素
子間分離を可能ならしめる半導体装置を提供せんとする
ものである。The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a semiconductor device that enables miniaturized isolation between elements.
本発明の方法はまず半導体基板を酸化して酸化膜を形成
し、フォトエツチング等によって酸化膜を選択エツチン
グし、さらにその上にシリコンのエピタキシャル成長を
行う。ただし、この場合普通酸化膜−J−には多結晶シ
リコン膜が、半導体基板表面には単結晶シリコン膜が成
長することは衆知である。次に、この上に粘度の低い(
30cp以下)のレジストを塗布する。こうするとレジ
ストは低粘度のもの程多結晶シリコン上では酸化膜の存
在により生じるステップのため単結晶シリコン上よりも
薄くなり、実際上、膜厚としては約1/3以下になる。In the method of the present invention, a semiconductor substrate is first oxidized to form an oxide film, the oxide film is selectively etched by photoetching or the like, and silicon is epitaxially grown on the oxide film. However, in this case, it is generally known that a polycrystalline silicon film grows on the oxide film -J-, and a single crystal silicon film grows on the surface of the semiconductor substrate. Next, on top of this, a low viscosity (
Apply a resist of 30 cp or less. In this way, the resist with a lower viscosity becomes thinner on polycrystalline silicon than on single crystal silicon because of steps caused by the presence of an oxide film, and in reality, the film thickness is about 1/3 or less.
次に、酸素プラズマにより多結晶ノリコン上のレジスト
だけをエツチングし、次に多結晶シリコン膜をエツチン
グし、その後、単結晶膜上のレジストを除去する。こう
することにより、酸化膜がシリコン基板上にうめ適寸れ
た形となり、\」法精度もよく、バーズビークのない素
子分離かできる。Next, only the resist on the polycrystalline silicon film is etched using oxygen plasma, then the polycrystalline silicon film is etched, and then the resist on the single crystal film is removed. By doing this, the oxide film can be filled with a suitable size on the silicon substrate, and the precision of the method is good, and device isolation without bird's beaks can be achieved.
以下、本発明の一実施例を図面に従ってさらに詳しく説
明する。第1図〜第6図は本発明に係る工程断面図であ
る。たとえばMOS−LSI の素子分離で説明する
と、第1図のようにp型(100)比抵抗8〜12 Q
−cmの半導体基板1に、チャンネルストップ用不純物
(硼素)のイオン打ち込みをB+、30KV 、2X
1013C,” −2の条件で行ない。Hereinafter, one embodiment of the present invention will be described in more detail with reference to the drawings. 1 to 6 are process cross-sectional views according to the present invention. For example, to explain the element isolation of MOS-LSI, as shown in Figure 1, p-type (100) resistivity is 8 to 12 Q.
-cm semiconductor substrate 1, channel stop impurity (boron) is ion implanted at B+, 30KV, 2X
1013C,” carried out under the condition of -2.
ついで、この基板1を、酸化雰囲気(1000℃。Next, this substrate 1 was placed in an oxidizing atmosphere (1000° C.).
パイロジェニック酸化H2102−72/40)中で処
理し、同表層部に酸化膜2を10μmの厚さに形成する
と同時にp+形拡散層3を形成する。次に、第2図のよ
うに、フォトリソグラフィによりレジストハターンを形
成し、リアクティブイオンエツチングにより酸化膜2を
エツチングする。この後、第3図のように、酸化膜2の
パターンを介して、基板1上にエピタキシャル成長を行
なう。このとき酸化膜2上には、多結晶シリコン膜4が
08μmの厚さに、基板1表面には単結晶シリコン膜6
が08μmの厚さに成長する。シリコン層4,50表面
不純物濃度は基板濃度にほぼ等しいものとする。寸だ、
単結晶シリコン膜5は酸化膜2よりも薄いものでなけれ
ばならない。なぜなら厚い場合には酸化膜2.シリコン
膜5の境界付近では一部酸化OI2」−で単結晶になる
ためで、エツチングに影響するためである。An oxide film 2 with a thickness of 10 μm is formed on the same surface layer, and at the same time a p+ type diffusion layer 3 is formed. Next, as shown in FIG. 2, a resist pattern is formed by photolithography, and the oxide film 2 is etched by reactive ion etching. Thereafter, as shown in FIG. 3, epitaxial growth is performed on the substrate 1 through the pattern of the oxide film 2. At this time, a polycrystalline silicon film 4 with a thickness of 0.8 μm is formed on the oxide film 2, and a single crystal silicon film 6 is formed on the surface of the substrate 1.
grows to a thickness of 0.8 μm. It is assumed that the surface impurity concentration of the silicon layers 4 and 50 is approximately equal to the substrate concentration. It's a size.
Single crystal silicon film 5 must be thinner than oxide film 2. This is because the oxide film 2. This is because near the boundary of the silicon film 5, a portion of the oxidized OI2'' becomes a single crystal, which affects etching.
次に第4図のように、エピタキシャル成長を行なった表
面に粘度の低い、たとえば30cp以下のレジスト6を
塗布する。この場合シリコン膜5」二のレジスト6の■
草原は8000人ぐらいとなり、多結晶シリコン膜4上
で2000〜3000人と約1/3となり、このレジス
ト6は、第5図のように、02プラズマによってこの多
結晶シリコン膜4上のレジスト6を取り除く。この場合
、単結晶シリコンl尊5−ヒで5000〜6000八と
なる。さらに、この単結晶シリコン膜6上でのレジスト
膜厚を厚くするためには、さらに粘度の低いレジスト(
30cp以下)を用いることが有効である。これば1/
jmの多結晶シリコン膜をとり除くためのマスクとして
必要なレジスト膜厚を考えると少なくとも5000〜6
000Å以上は必要だからである。次に残ったレジスト
6をマスクとして、酸化膜2」−の多結晶シリコン膜4
をプラズマエツチングする。Next, as shown in FIG. 4, a resist 6 having a low viscosity, for example, 30 cp or less, is applied to the epitaxially grown surface. In this case, the resist 6 of the silicon film 5'' is
There are about 8,000 people on the grassland, which is about 1/3 of the 2,000 to 3,000 people on the polycrystalline silicon film 4, and the resist 6 on the polycrystalline silicon film 4 is removed by the 02 plasma as shown in FIG. remove. In this case, the value of single crystal silicon is 5,000 to 6,000. Furthermore, in order to increase the thickness of the resist film on this single crystal silicon film 6, it is necessary to use a resist with a lower viscosity (
30 cp or less) is effective. This is 1/
Considering the resist film thickness required as a mask to remove the polycrystalline silicon film of jm, it is at least 5000~6.
This is because a thickness of 000 Å or more is necessary. Next, using the remaining resist 6 as a mask, the polycrystalline silicon film 4 of the oxide film 2''
plasma etching.
そして、最後に、第6図のようにレジスト6をとり除い
て、素子分離が完成する。こうして、単結晶ノリコン層
5の部分は、酸化膜2で分離され、この部分にMO3+
−ランジスタが形成可能になる。Finally, as shown in FIG. 6, the resist 6 is removed to complete element isolation. In this way, the portion of the single crystal noricon layer 5 is separated by the oxide film 2, and this portion has MO3+
- transistors can be formed;
以」二の工程はチャンネルストノ・々−用のp+1広散
層3を除けば、バイポーラトラン/スタの素子分離にも
応用できる。The following two steps can also be applied to device isolation of bipolar trans/stars, except for the p+1 diffusion layer 3 for the channel transistors.
本発明によれば、レジストパターン寸法通りに素子分離
ができ、かつ素子分離用の酸化膜は単結晶シリコン中に
埋込まれた形となるため、表面か平坦となり、寸だ、選
択酸化でみられるようなノく−ズビークもないことから
、本発明は素子分離方法として非常に有効なものである
。According to the present invention, elements can be isolated according to the resist pattern dimensions, and since the oxide film for element isolation is embedded in single crystal silicon, the surface is flat and can be easily achieved by selective oxidation. The present invention is very effective as an element isolation method because there is no noise beak that would otherwise occur.
【図面の簡単な説明】
第1図〜第6図は本発明に係る方法を示す工程断面図で
ある。
1・・・・・・半導体基板、2・・・・・・酸化膜、4
・・・・・・多結晶シリコン層、5・・・・・・単結晶
シリコン層、6@・1II11レジスト層。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 6 are process cross-sectional views showing the method according to the present invention. 1... Semiconductor substrate, 2... Oxide film, 4
. . . Polycrystalline silicon layer, 5 . . . Single crystal silicon layer, 6@.1II11 resist layer.
Claims (2)
前記酸化膜を選択開口して、前記半導体基板表面を露出
する工程と、気相成長法により前記半導体基板露出面に
エピタキシャル成長半導体単結晶膜、前記酸化膜上に半
導体多結晶膜を、それぞれ、同時に成長する工程と、全
面に7オトレジストを塗布する工程と、前記多結晶膜上
のフォトレジストを除く工程と、前記多結晶膜を残存し
た前記レジストをマスクとして途去する工程とを含むこ
とを特徴とする半導体装置の製造方法。(1) forming an oxide film on one main surface of the semiconductor substrate;
selectively opening the oxide film to expose the surface of the semiconductor substrate, and simultaneously growing an epitaxially grown semiconductor single crystal film on the exposed surface of the semiconductor substrate and a semiconductor polycrystalline film on the oxide film by vapor phase growth. A step of growing the photoresist, a step of applying a photoresist on the entire surface, a step of removing the photoresist on the polycrystalline film, and a step of removing the resist with the remaining polycrystalline film as a mask. A method for manufacturing a semiconductor device.
る(2) The viscosity of the photoresist is 30 cp or less
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12641482A JPS5916340A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12641482A JPS5916340A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5916340A true JPS5916340A (en) | 1984-01-27 |
Family
ID=14934571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12641482A Pending JPS5916340A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5916340A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0366035U (en) * | 1989-10-26 | 1991-06-27 | ||
US5045494A (en) * | 1989-05-10 | 1991-09-03 | Samsung Electronics Co., Ltd. | Method for manufacturing a DRAM using selective epitaxial growth on a contact |
US5096844A (en) * | 1988-08-25 | 1992-03-17 | Licentia Patent-Verwaltungs-Gmbh | Method for manufacturing bipolar transistor by selective epitaxial growth of base and emitter layers |
-
1982
- 1982-07-19 JP JP12641482A patent/JPS5916340A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5096844A (en) * | 1988-08-25 | 1992-03-17 | Licentia Patent-Verwaltungs-Gmbh | Method for manufacturing bipolar transistor by selective epitaxial growth of base and emitter layers |
US5045494A (en) * | 1989-05-10 | 1991-09-03 | Samsung Electronics Co., Ltd. | Method for manufacturing a DRAM using selective epitaxial growth on a contact |
JPH0366035U (en) * | 1989-10-26 | 1991-06-27 |
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