JPS59161917A - Sequential parallel type analog/digital converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter and multiplier which works stably without increasing hard quantity by using sequentially parallel comparison type A/D converters in terms of time division. CONSTITUTION:An input analog signal Vin is compared with the comparison voltage by seven comparators 20. At first the reference voltage VREF and the earth potential are applied to both terminals 30 and 31 of a series capacitor train. Then the comparison voltage is generated from each juncture between capacitors. A switch is selected by an EXOR26 and an AND27 and on the basis of the first comparison result, and the electric charge is accumulated at a sampling/holding circuit 28. The reference voltage of the next stage is generated at the output terminals of integration circuits 29 and 29', and the comparison of the next stage is carried out. Then the reference voltage is generated in the same way, and the comparison is carried out for the 3rd and 4th stages. An A/D converter can be applied to a counter of a multiplier.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a successive-parallel type AD converter constituted by a Swiss capacitor (SC) circuit. In particular, it is a serial-parallel type that takes advantage of the characteristics of both conventional sequential and parallel AD converters. This invention also relates to an AD converter that can ideally be used repeatedly to quantize any number of bits.

Recently, with the demand for large-scale integration of not only digital circuits but also analog circuits, switched capacitor (SC) technology based on MO3 integration technology has been attracting particular attention. This sC technology uses AD conversion or DA, which is necessary when performing digital image processing and signal processing.
Not only can it be applied to conversion processing systems, but it can also be used in analog calculation circuits.
), emphasis has been placed on expansion to other applications. In this case, SC can be achieved by replacing the resistance of a conventional converter or arithmetic circuit with a switch and a capacitor, but similar to SCF using time division multiplexing, it is possible to use It is expected that high-performance converters and arithmetic circuits can be created by skillfully utilizing the unique SC technology.

In the past, there has been research attempting to convert converters and arithmetic circuits into SCs. For example, as an AD converter, a parallel comparison type has the disadvantage that as the number of bits of a digital signal increases, the number of comparators increases and the total amount of hardware increases, so a sequential type has been proposed. However, the successive AD converter has the disadvantage of being slow because its output is bit serial. As an application of the D to D converter, for example, an analog multiplier can be considered. As an analog multiplier, both voltages are AD converted and multiplied using a digital multiplier,
Since it is sufficient to convert the result to DA, this results in the problem of converting the DA converter to SC. However, this method requires a digital multiplier, so
Finding a suitable match between converter and multiplier becomes difficult. For example, if one of the AD converters is a sequential type, its output is output from the MSB, but the bit serial input of a sequential type multiplier based on Booth's algorithm is the LS.
It is necessary to input from B, which causes inconsistency. Also,
If the AD converter is of the parallel comparison type, the digital multiplier should also be of the parallel type using a combinational circuit, but this not only limits the number of bits but also increases the heart size of both the digital and analog parts. Put it away.

The present invention eliminates such conventional drawbacks and proposes a new serial-parallel type AD converter that is faired by an SC circuit,
As an application, we propose a method for configuring an analog multiplier. This multiplier does not use a digital multiplier and is composed of an AD converter, a coefficient unit, and an encoder. The operation is to AD convert one voltage at high speed, control the switch of the coefficient multiplier with the digital output signal, and use the encoder to determine the sign of the product of the other voltage manually input to the coefficient multiplier. This is what is output. The proposed 8-digit converter is a sequential parallel type that takes advantage of the features of both conventional sequential and parallel AD converters. This is an IN-PLACE method that is repeatedly used many times in a time-division manner. Ideally, any number of bits can be quantized, so it can be expected to be effective as a single AD converter with high precision and high speed. In addition, these circuits use voltage follower type operational amplifiers for the integrator, etc., similar to SCFs using unity gain sofas that have been attracting attention recently, so they operate stably without feedback deviation due to switching. AI that can
We propose a converter and a multiplier constructed by extending it.

The present invention is characterized by: a reference voltage dividing means which receives the reference voltage difference in the previous stage at both ends and divides the reference voltage difference between the two ends into n equal parts; is connected to a parallel comparator circuit, one input of which receives the input voltage in common, and the other of which receives the divided voltage, and the output of the parallel comparator circuit, and when the output logic states of the adjacent comparator circuits are different. Controlled by the output of the logic circuit, the reference voltage difference in the next stage is set to l/of the reference voltage difference in the previous stage. It is an object of the present invention to provide a successive parallel type analog-to-digital converter, characterized in that it has means for multiplying the electric reference voltage by 1 and supplying the voltage to both ends of the electric reference voltage dividing means.

Next, the present invention will be explained with reference to the drawings. AD of the present invention
The converter is a serial-parallel type that takes advantage of the characteristics of both conventional sequential and parallel type AD converters, but an AD converter with these characteristics has been developed as part of an SC multiplier as an applied patent. Let me explain.

SC configured by applying the AD converter proposed in the present invention
A block diagram showing the flow of signals between each unit of the multiplier is shown in FIG.

The encoder 1 has two functions, one of which is to determine the sign of the input voltage .chi., and the other to output the absolute value of the input voltage. That is, when the input voltage Vx is positive, the encoder 1 inputs the sign bit φ
Set the sign bit Φ0 so that 0 becomes 0 and Φ0 becomes 1 when negative.
output and control the switch of the 8-'' circuit.
Also, the absolute value of the input voltage, 1v, becomes the input voltage of the AD converter.

The AD converter °2 uses the IN-PL8E method, in which hardware that only has a 3-bit quantization function is used repeatedly in a time-division manner by switching control, so the decoder signal is Three bits are output from the top.

The coefficient unit 3 consists of a B-'A circuit 30 and a 3-bit coefficient circuit 31. The circuit 30 synchronizes B-'I' with the output of the AD converter 2 and calculates 1×vf for the input voltage 1.

This is a circuit where the equations are 1/8×■t, 1/64×vt, and so on. The output voltage of this 8-pile circuit 30 is 8-^×
(2) When inputting 1 to the 3-bit coefficient circuit 31G2, an analog output of the V-factor XV7 is obtained under the constraints of ζ and the like by switching control using the digital signal vF for each 3 bits from the 8-digit converter 2.

Next, we will describe the operating principle of the basic circuit, which is important for explaining a successive parallel AD converter using an SC circuit and a multiplier as its application.

The basic circuit of a voltage follower is shown in Figure 2. Ideally, Eout = Ein, the large impedance is infinite, the output impedance is zero, and the frequency band where the gain is 1 is extremely wide. have characteristics. When a basic circuit such as an SC integrator or an SC adder is configured using only this voltage follower, the feedback route does not include a switch, so the feedback does not shift when the switch is turned off, and the entire SC circuit operates stably. Are known.

Figure 3 shows a sample and hold circuit using a voltage follower. First, when the switch S is ON, the input voltage Vi
n is the charge CV on the capacitor C through the voltage follower,
When the next S turns off, g turns on.
Therefore, the voltage Vin appears at the output while the capacitor voltage - is held.

The coefficient circuit is as shown in FIG. 4(a), and is a circuit that is the basis of the operating principle of the adder and integrator, which will be described later.

It is assumed that the capacitor CO has a charge of Coco as an initial value. First, when S is ON, a charge called CIVin is accumulated in CI. In this state, the output voltage Vo is Un
It is. Next, when S turns OFF and 100 turns ON at the same time, the electric charge stored in the capacitor C1 is completely discharged so that the voltages across CI become equal, that is, the electric charge becomes zero (□). Then, as shown in FIG. 4(1)), the charges C1, V- move to the capacitor CO. At this time, Kirlhoff's current law is, if time delay is ignored, CI (-V'11, 0) = Co (Vo V)
...(ll). The voltage of the capacitor CO when the bell is turned on is: ■= (CI/Co)■7.+■o......,,(
2), and the output ■0 of the voltage follower is ■ ・■ Therefore, when the initial value ■0 is zero, the input voltage Vi@ is
A voltage multiplied by +/Co is output.

If the coefficient circuit described above is expanded, an adder as shown in FIG. 5 will be constructed. Assume that there is no charge in the capacitor Go in the initial state. When S is ON, capacitor CI,
C2,...,Cn are CIVl, C2 depending on the input voltage.
V2. '..., CnVn are charged respectively, and when S turns off and S turns on at the same time, CI,
The charges stored in C2...Cn are discharged and all move to the capacitor Co. After that, the output voltage Vn of the voltage follower is the value Vo=, Σ(Cλ/Co)■) (3)
becomes.

The integrator is a circuit in which the switch of the coefficient circuit in Figure 4 is removed, and the charge transferred to the capacitor Co is set to the initial value for the next cycle without being discharged, and the integration is performed by repeating the operation. Execute. That is, Vo (kT+T)=(C+/C,o)vi,+
(C+/Co)VO(kT)・・・・・・・・・(4
), the output vO of the voltage follower is obtained.

However, kT is an arbitrary discrete time, and T is the period of the integrator.

It is clear that the integral adder is a circuit obtained by removing the switch of the adder shown in FIG.

Next, the configuration and operation of each unit circuit of a sequential parallel multiplier using an SC circuit as an application of the AD converter of the present invention will be described.

The encoder shown in FIG. 6 has two functions, one of which is to determine the sign of the input voltage V<, and the other is to output the absolute value of the input voltage V<1. It is. The sign determination circuit 10 is inside the upper dotted line in FIG. Input voltage Vχ is the ground potential and comparator 10
0, and its output is latched by the launch circuit 101, and the sign hit Φ0 becomes .
Output from output. The absolute value i is within the dotted line at the bottom of Figure 6.
This is the power circuit 11. When the switch SO is ON, an input voltage V is applied to the capacitor C, and a charge CV:t is stored in the capacitor C. At this time, for example, if 〉0 is set, the output Q of the flip-flop is ONL and the output is 0, so the switch Q is turned on and the switch is turned off. Next, when SO turns OFF and SL turns ON, switch Q is still active.

Since the state of the stone remains unchanged, the lower side of capacitor C is grounded. Therefore, the output voltage is l vx l = V
.

becomes. ■3 When it is 0, the polarity of the charge on the capacitor C is reversed, but since the switch Q is OFF and Q is ON, the negatively charged plate, that is, the upper side, is still grounded, and the output voltage is 1■χ 1- -vx.

Note that since the output is connected to the input of the comparator inside the AD converter, there is no buffer on the output side.

Next, we will explain in detail the successive-parallel input converter, which is the basic patent of the present invention. A circuit diagram explaining the principle is shown in Fig. 7. The part surrounded by dotted lines is a parallel type that has been commonly used in the past, and points a and b.

C each I/4. V2/4. V
P...

The potential is 3/4 Vptp. In a conventional AD converter alone, the potential at each point is compared with the input voltage V? with the comparator 20, and the result is sent through the priority circuit 21. It is launched in the launch circuit 22, encoded in the encoder 23, and output.This conventional method can perform AD conversion at very high speed, but as the number of bits increases, the number of comparators increases, and quantization The level is fixed at, for example, l/4.VRBF, and comparison with a voltage lower than that will result in a quantization error and accuracy cannot be improved.

Therefore, in this 8D converter, as shown in FIG. 7, by controlling the switching of the next-stage reference voltage selection circuit 24 and the feedback circuit 25, the quantization level is adjusted to 1/2, for example.
4. VlT%P, 1/16, -, 1/6
It is possible to make it as small as 4 pieces...

In the circuit of FIG. 7, the reference voltage is now 4V, the input voltage Vi+ is 2.6V, and the switch S1. S2 is on the right (
11], the comparator output is GO.
MPI, 2 is a high level, and C0M3 is a low level. If the quantization level is L/4 V, P, i.e. I
It is V. Now, since COMP2 is at high level and C0M3 is at low level, the input voltage is always turned on (2
) and the potential at point C (3■).

Therefore, the output of the comparator is input to the next stage reference voltage, and switching control is performed so that the reference voltage becomes IV. That is, if Sl and S2 are turned to the feedback circuit 25 side, and at the same time a voltage of 3V is applied to Sl and 2V is applied to S2 through the feedback circuit 25, and this state is maintained, the bottom potential of the series resistor string becomes 2V.
At ■, a potential difference of 1■ is applied. If we compare again using the comparator 20, the quantization level at this time is 1/4 V, -1/4 (1/4 V,
), that is, 0.25 V. If the above feedback operation is repeated, the quantization level will be reduced to 1/4 each time.
This enables more accurate AD conversion.

The AD converter using the SC technology proposed in the present invention has, for example, an output of 3 bits each, and may be a series resistor, but in this case, the series resistor is replaced with a capacitor string connected in series with a parallel circuit of capacitors and switches, and multiplication is performed. Since the launch circuit 22 and encoder 23 are unnecessary when configuring the device, the configuration does not include them. A configuration diagram of this AD converter is shown in FIG.

In FIG. 8, the comparator output 200. EX-OR
26, AND27. The flow from the gate of the switch S hits the reference voltage selection circuit 24, and the sample and hold circuit 28. The flow from the integrator circuit 29, 29', the top point 30 and the bottom point 31 of the series capacitor hits the feed bank circuit 25.

EX-OR 26 detects the difference in the output level of the upper and lower adjacent comparators. A N D 27 prevents malfunctions due to differences in response times of the comparators.

Respectively l/8 奄p, 2/8%*,..., 7/
8V...

Only one of the switches connected to the potential point is turned on by the AND output. (If 3/8 v*i
p) S&H circuit 28 is 3/8 X4L,
.

3 / to capacitor C without changing the potential at the potential point of
8 Import V2sp. Lower circuit 2 divided into upper and lower parts
9' is a voltage holding circuit and connects 3/8■7 to the lowest point of the capacitor row.
, outputs. The upper circuit is the above-mentioned integrating circuit, in which case the initial value is 3/8V, V and M correspond to Vpg, and the formula (
4) outputs 4/8V to the capacitor row Mogami. Therefore, a voltage that is 1/8 of the reference voltage at the previous stage is applied to the capacitor array. A capacitor C' added below the lowest point 31 of the capacitor array is for preventing the capacitor array from floating above ground due to switching operation.

Use the clock shown in the figure and set the initial reference voltage %a
For example, p is set to 5 [■]. From this value, the quantization level at the first comparison is 1/8・5 = 0.625 [V]
・・・・・・・・・(6) Second comparison 1/64・5= 0.781xlO' [
It will be compared using a value like V]. The experimental results are shown in FIG. This waveform shows two phenomena: the output of the buffer of the upper integration circuit 29 and the input voltage V. By looking at the waveform at this point, +11 S &
Input operation of voltage at each potential point to H circuit +21 S &
Two operations can be confirmed: the output voltage of the H circuit +1/8 VtKP. Clock time, interval 1
1, ■2, . . . Ie, compare the circuit operation at each time and interval with the operation waveform in FIG.

The straight line near the center of the diagram represents the input voltage V1w,
It shows 0.24 [V]. At this time, since the quantization level is 0.625 [V], the output of the first S&I (circuit 28) should be zero.The first output is in time interval I2, but see the photo. 1/8 VpεF is applied to the output of the S&H circuit 28 at i3.

In the figure, the voltage has actually increased by about 0.62 [V]. In other words, it can be seen that the gap is correctly 1/8 vp. ■5
When , the circuit operation is the second output of the S&H circuit.

In the photo, it is shown as 0.22 [V].

This shows that the second S&H circuit had a voltage of 0.22 [V]. Furthermore, 1/64V*ap should be added at I6, but in the figure it is actually 0.0781 [
0.08[V] (= 1/64V, tP)
] You can see that it is placed in a fixed position. At the third output of the S & H circuit 28 of Ie, the voltage is 0.23 [V, ] in the figure.
It shows.

As mentioned above, the output of the S&H circuit 28 gradually becomes closer to the input voltage, and is exactly 1/8 V,..., 1/6
4■15. This figure shows that the concept of circuit operation was correct because the Note that A of the present invention
The D converter is 30[K11z] to 30[K11z] for commercially available ICs.
Although it has been confirmed that the circuit operates accurately at a basic clock frequency of 11z], it is expected that it will be possible to achieve much higher speeds if it is implemented on a chip.

Next, FIG. 10 shows a coefficient unit 3 of a multiplier made by applying the 8-digit converter of the present invention. The coefficient unit 3 receives the input voltage 8-'
It is composed of two parts: a multiplier circuit section 30 and a 3-bit coefficient circuit section 31. First, the operating principle of the input voltage octupling circuit 30 will be explained. Switch Φ0. The operation of Φ0 is as follows from the explanation of encoder 1 above: (i) When Vt>0, Φ・ is O
N, Φ is OFF, (ii) Φ is ON when V voice <0,
φ is OFF. Furthermore, when the switch S1 is turned on, one of these states is already in place.

(i) When Vz>O, φ is ON) Switch So.

Due to the operation of Si, a charge of 8CVf has already been accumulated in the capacitor 8C when Sl and S3 are turned on. If you rewrite the circuit diagram, it will look like Figure 11 (81), and at this time, through the buffer ■. -+ = I
V) appears, and at the same time a charge of 7C appears on the capacitor 7C.
V,1 is accumulated. Next, when S3 is turned off and 84 is turned on at the same time, the circuit becomes as shown in FIG. 11 fbl. At this time, the charge in the capacitor 7C is forcibly discharged by the function of the buffer, and moves to the capacitor 8C following the route shown in the figure. And considering the polarities of the mutual charges that had been accumulated, it ended up being ■. ,,j is 1. /8XV1
becomes. Then °ζ switches S3 and 84 are turned on alternately again.
Then, an output of 1/64xV2 is obtained. By repeating the above operations, the input voltage is increased by 8-' times.

(ii) When Vl<0 (Φ is ON), the charge of capacitor 8C is opposite to when the previous gate is ON,
Since the plate side on which negative charges are accumulated is connected to the buffer, Vo-t = IX%. The subsequent operation can be considered in the same way as when ■D 〉0, and in the end, V6h'
t is -1/8XV, -1/64xV, and the output is 1
η is rejected.

Next, the 3-bit coefficient circuit 31 will be explained.

This is basically the structure of the adder described above, but the input voltage is the output φ2゜Φ2...
It is controlled by Φ7. That is, the number of H level outputs of the AD converter 2 and the voltage of 8-'AX Vf of the open can are input.

Furthermore, the relationship between the quantization level of the output of the AD converter 2 and the output voltage of the 8x circuit 30 by -1 is based on the initial reference voltage.
When the quantization level is 1/8 V, F, ■
aut = 1/8'AV (n = 0,
1, ...) The timing is like a thousand.

Next, the algorithm of this multiplier is shown. AD converter 2
The output of (11) tun = Oorl (where i = 1 mi 2,...7, n =
1.2,...), which means the nth output of the i-th comparator. If the input voltage of the encoder 1 is Vt, the input of the -AD converter 2 is 1vxl. Considering the output method of the AD converter 2, it can be expressed as follows. Also, from the operating principle of the coefficient multiplier, the coefficient multiplier=sc''y'at From equation (7), equation (8) is 1Vxl=Vx' (7) When V.

-V when IVxl=Vx.

Since we will perform the following operation, taking into account the sign of ■χ, we will rewrite 1 to Vt and get ;, Vo-C'/ CVI? EF Vc
×Vy Here, if c'=cvRεF, then 1, °, Vo total=■××■y (10). That is, by setting the capacitance of C' to CVt:hH, multiplication is performed isometrically.

Next, a timing chart considering the entire multiplier is shown. (See Figure 12) This shows up to three multiplication outputs, and if three or more outputs are required, So.
Sl, S2. Ss remains unchanged, and 33, Sa, and S* can be repeated as shown in the figure.

Effects of the present invention The successive parallel type AD converter of the present invention is an IN-PLACEA.
By adopting the D conversion method, we have created a completely new type of AD converter that can expand the number of output bits. Because it supports high-precision conversion and is fast conversion,
It can be said that this AD converter has overcome the drawbacks of conventional AD converters. In addition, the switch 1-゛・capacitor・analog multiplier configured by applying this AD converter includes an encoder,
It combines three things, an AD converter and a coefficient multiplier, and multiplies two analog signals isometrically, which has the effect of eliminating the need for a digital multiplier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an SC multiplier using the AD converter of the present invention, FIG. 2 is a basic circuit of a voltage follower circuit, and FIG.
Figure 4 shows the basic circuit of a sample bold circuit, Figure 4 shows the basic circuit of the coefficient circuit, Figure 5 shows the basic circuit of the adder, Figure 6 shows the details of the encoder used in the SC multiplier of the present invention, and Figure 7 shows the basic circuit of the sample bold circuit. The figure is an explanatory diagram of the AD converter of the present invention, Figure 8 is a detailed diagram of the AD converter of the present invention, Figure 9 is an operation waveform diagram of the AD converter of the present invention, and Figure 10 is the SC multiplication of the present invention. Detailed diagram of the coefficient unit of the device,
11 is an 8-E multiplication circuit inside the coefficient multiplier, and FIG. 12 is a timing diagram of the present invention. 20... Comparator, 26... EX-O
R circuit, 27...AND circuit, 28...sample hold circuit, 29.P-integrator, 2
9′... Coefficient unit, 3°... Capacitor row top point, 31... Capacitor row bottom point, So, S
l, S2. '33°Sd, 35. S6...Switch, C...Capacitor Patent applicant 1) Chuo Patent attorney Okan Yoshinoki 1 l'lI, Yu face μ----------++ + +
-+6th eye Figure 71

Claims (2)

[Claims] (1) A reference voltage dividing means that receives the reference voltage difference from the previous stage at both ends and divides the reference voltage difference between the two ends into n equal parts, and is connected to the output of the voltage dividing means, each having one input in common. The other side receiving the input voltage is connected to a parallel comparison circuit receiving the divided voltage and the output of the parallel comparison circuit, and is activated only when the output logic states of the adjacent comparison circuits are different, and the output logic state is activated. is controlled by a logic circuit that inactivates all of them if they are the same, and the output of the logic circuit, and the reference voltage difference in the next stage is made 1/n times the reference voltage difference in the previous stage, and the reference voltage difference in the previous stage is and means for supplying voltage to both ends of the voltage dividing means. (2) A patent in which one voltage is AD converted at high speed by the analog-to-digital converter, the digital output signal controls the switch of a coefficient multiplier, and the product with the other voltage input to the coefficient multiplier is output. An analog multiplier comprising the analog-to-digital converter according to claim 1.