JPS59161852A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59161852A
JPS59161852A JP58035338A JP3533883A JPS59161852A JP S59161852 A JPS59161852 A JP S59161852A JP 58035338 A JP58035338 A JP 58035338A JP 3533883 A JP3533883 A JP 3533883A JP S59161852 A JPS59161852 A JP S59161852A
Authority
JP
Japan
Prior art keywords
layer
bonding
passivation film
wire
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58035338A
Other languages
Japanese (ja)
Inventor
Tsunemitsu Koda
國府田　恒充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58035338A priority Critical patent/JPS59161852A/en
Publication of JPS59161852A publication Critical patent/JPS59161852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the corrosion resistance of a pad exposed surface which has been heretofore completely defenseless to corrosion by a method wherein the Al surface of a bonding pad uncovered with a bonding wire is oxidized and thus changed into a passivation film made of Al2O3. CONSTITUTION:An Al wiring contact layer 3' is formed on a semiconductor substrate 1', and the exposed part of said layer is covered with a passivation film 2'. Next, an aperture is bored in this film 2', and the bonding wire 4' is bonded to said layer 3'; at this time, the layer 3' exposed around the wire 4' is not left as it is, but applied to the following treatment. Namely, the layer 3' is changed into an Al2O3 film 5 with volume expansion by performing anodic electrolytic oxidation to said layer 3', thereby surrounding the pad part of the wire 4', and accordingly the surface of the layer 3' is passivated.

Description

【発明の詳細な説明】 本発明は半導体装置の構造に関するものである。[Detailed description of the invention] The present invention relates to the structure of a semiconductor device.

高度な信頼性を要求される半導体装置においては、従来
よりその表面に何らかの手法を用いてパッシベーション
膜を設ける事によシ信頼度の向上を実現して来た。しか
しながら、従来の構造では、そのボンディング・パッド
部にパッシベーション膜は存在せず半導体装置の中でも
、小型かつ樹脂封入のパッケージを持つものでは、特に
問題となる。即ち小型で樹脂封入のパッケージにおいて
は、その不良の大半がポンディングパッド部のアルミニ
ウムの配線露出部分からのアルミニウムの腐食によるも
のである事が確認されている。In semiconductor devices that require a high level of reliability, improvements in reliability have conventionally been achieved by providing a passivation film on the surface of the device using some method. However, in the conventional structure, there is no passivation film in the bonding pad portion, which is a particular problem in semiconductor devices that are small and have resin-filled packages. That is, it has been confirmed that most of the defects in small, resin-filled packages are due to corrosion of aluminum from the exposed aluminum wiring portions of the bonding pads.

本発明は、このような樹脂封入によるパッケージで、そ
の耐食性が問題となるような半導体装置の信頼度の向上
を計るためになされｋものである。The present invention has been made in order to improve the reliability of semiconductor devices in which corrosion resistance is a problem with such resin-filled packages.

即ち従来の半導体装置においては、そのポンディングパ
ッド部にはパッシベーション膜は存在せず、ボンディン
グ線以外の部分はアルミニウムの配線が露出しており、
腐食に対しては全くの無防備であった。In other words, in conventional semiconductor devices, there is no passivation film in the bonding pad portion, and aluminum wiring is exposed in areas other than the bonding lines.
It was completely defenseless against corrosion.

そこで本発明は、ボンティング線によって覆われていな
い部分のボンディング・パッド部のアルミニウム表面を
何らかの方法によって酸化する手によってその表面にア
ルミナ層を成長させ、パッシベーション膜の機能を有せ
しめる事とした。これは例えば半導体装置をリードフレ
ームに固定しボンディングを行った状態で陽極電解酸化
を行う事によりて実現できる。このようにし７て得られ
た半導体装置は、その表面にアルミニウムが露出してお
らず良好な耐食性を示す。従って、このような構造を採
用する事によって、大巾な耐食性の向上、ひいては信頼
度の向上が可能となる。Therefore, in the present invention, an alumina layer is grown on the aluminum surface of the bonding pad portion not covered by the bonding wire by oxidizing it by some method to provide the function of a passivation film. This can be achieved, for example, by performing anodic electrolytic oxidation while the semiconductor device is fixed to a lead frame and bonded. The semiconductor device obtained in this manner has no exposed aluminum on its surface and exhibits good corrosion resistance. Therefore, by adopting such a structure, it is possible to greatly improve corrosion resistance and, in turn, improve reliability.

次に図面を用いて説明する。Next, it will be explained using drawings.

第１図の従来の半導体装置の基板１の表面には配線及び
外部とのコンタクト用のアルミニウム層３が存在してい
る。このアルミニウム層３の表面は物理的あるいは化学
的方法によって形成されたパッシベーション膜２によっ
て覆われているが、第１図に示したように、ボンディン
グ・パット部においてはボンディング線４によって覆わ
れている部分以外はアルミニウム層３が露出している。An aluminum layer 3 for wiring and contact with the outside exists on the surface of a substrate 1 of the conventional semiconductor device shown in FIG. The surface of this aluminum layer 3 is covered with a passivation film 2 formed by a physical or chemical method, and as shown in FIG. 1, the bonding pad portion is covered with a bonding line 4. The aluminum layer 3 is exposed except for the portion.

第２図の実施例では、１′は半導体装置基板、２′は物
理的もしくは化学的方法によって形成したパッシベーシ
ョン膜、３′は配線及びコンタクト用のアルミニウム層
、４′はボンディング線である。以上は従来の半導体装
置と同様である。５は陽極醒解酸化等によって形成した
アルミナ層であシ、このようなアルミナ層の形成により
アルミニウム層の露出部分はなくなシこれに伴い耐食性
が向上する。In the embodiment shown in FIG. 2, 1' is a semiconductor device substrate, 2' is a passivation film formed by a physical or chemical method, 3' is an aluminum layer for wiring and contacts, and 4' is a bonding line. The above is the same as the conventional semiconductor device. Reference numeral 5 is an alumina layer formed by anodic deoxidation or the like. By forming such an alumina layer, there is no exposed portion of the aluminum layer, thereby improving corrosion resistance.

【図面の簡単な説明】 第１図は従来の半導体装置のボンティング・、＋ラド部
の概略断面図、第２図は本発明ＶＣよる半導体装置のボ
ンデインク・パッド部の概略断面図である。 １．１′・・・・・・♀鋳体基板、３．３’・・・・・
・アルミニウム層、５・・・・・・パッシベーション膜
。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view of the bonding and +rad portions of a conventional semiconductor device, and FIG. 2 is a schematic sectional view of the bonding ink pad portion of a semiconductor device according to the VC of the present invention. 1.1'...♀Cast substrate, 3.3'...
- Aluminum layer, 5... Passivation film.

Claims (1)

【特許請求の範囲】[Claims] ボンディング線を除くボンティングバット部にパッシベ
ーション膜を有する事を特徴とする半導体装置。A semiconductor device characterized by having a passivation film in a bonding butt portion excluding a bonding line.
JP58035338A 1983-03-04 1983-03-04 Semiconductor device Pending JPS59161852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58035338A JPS59161852A (en) 1983-03-04 1983-03-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58035338A JPS59161852A (en) 1983-03-04 1983-03-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59161852A true JPS59161852A (en) 1984-09-12

Family

ID=12439054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58035338A Pending JPS59161852A (en) 1983-03-04 1983-03-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59161852A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387794B2 (en) 1995-07-14 2002-05-14 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
US6825512B2 (en) * 2000-08-11 2004-11-30 Thales Micromachined sensor with insulating protection of connections
US8403774B2 (en) 2009-04-01 2013-03-26 Nike, Inc. Golf clubs and golf club heads
US8786092B2 (en) 2005-06-17 2014-07-22 Rohm Co., Ltd. Semiconductor integrated circuit device
US8915794B2 (en) 2009-04-21 2014-12-23 Nike, Inc. Golf clubs and golf club heads
US9717959B2 (en) 2009-04-21 2017-08-01 Karsten Manufacturing Corporation Golf clubs and golf club heads

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387794B2 (en) 1995-07-14 2002-05-14 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
US6603207B2 (en) 1995-07-14 2003-08-05 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
US6825512B2 (en) * 2000-08-11 2004-11-30 Thales Micromachined sensor with insulating protection of connections
US8786092B2 (en) 2005-06-17 2014-07-22 Rohm Co., Ltd. Semiconductor integrated circuit device
US9041160B2 (en) 2005-06-17 2015-05-26 Rohm Co., Ltd. Semiconductor integrated circuit device
US8403774B2 (en) 2009-04-01 2013-03-26 Nike, Inc. Golf clubs and golf club heads
US8801543B2 (en) 2009-04-01 2014-08-12 Nike, Inc. Golf clubs and golf club heads
US8915794B2 (en) 2009-04-21 2014-12-23 Nike, Inc. Golf clubs and golf club heads
US9717959B2 (en) 2009-04-21 2017-08-01 Karsten Manufacturing Corporation Golf clubs and golf club heads

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