JPS59161051A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59161051A JPS59161051A JP59027045A JP2704584A JPS59161051A JP S59161051 A JPS59161051 A JP S59161051A JP 59027045 A JP59027045 A JP 59027045A JP 2704584 A JP2704584 A JP 2704584A JP S59161051 A JPS59161051 A JP S59161051A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- film
- solder
- electrode
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は１個以上の回路素子を含む半導体基板上にチッ
プパッシペーショｚ＾を介して、たとえばＴ ｉ ／
Ｃｕの２層膜からなる配線導体を有し、かつその導体の
一部にハンダバンプを設けた半導体装置に関する。とく
に該ノ・ンダバンブを前記基板上に円状ならびに同心円
状に装置したことを特徴とする半導体装置に関する。さ
らに本発明はＩＣチップ内の電極パッドを、プラズマＣ
ＶＤ法による窒化シリコン膜を介して、チップの能動素
子領域上面に配置さ亡た構造の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor substrate containing one or more circuit elements via chip passivation, for example, T i /
The present invention relates to a semiconductor device having a wiring conductor made of a two-layer film of Cu and having solder bumps provided on a part of the conductor. In particular, the present invention relates to a semiconductor device characterized in that the semiconductor devices are arranged circularly and concentrically on the substrate. Furthermore, the present invention provides electrode pads within an IC chip with plasma C.
The present invention relates to a semiconductor device having a structure in which a silicon nitride film is disposed on the top surface of an active element region of a chip using a VD method.
以下、本発明を従来装置との比較によって説明する。The present invention will be explained below by comparison with a conventional device.
まず第１図に従来装置における配線導体およびハンダ電
極の形成方法を、ま−た第２図に従来の電極パッドの配
置をチップ表面から見た場合についてそれ七扛示す。第
１図ｔａ＋に示すように１回路索子を含む半導体基板１
上に第１の絶縁膜２を介して配置導体３を形成し、さら
に該配線導体３上に第２の絶縁膜４すなわちチップパッ
シベーション膜を形成する。次に該チップパッシベーシ
ョン暎４に通常のホトレジ処理および化学的エツチング
によって開孔５を設け、つぎにＴｉ６・Ｃｕ７の順にそ
ｎぞれ所定厚さだけ全面的に被着する。First, FIG. 1 shows a method of forming wiring conductors and solder electrodes in a conventional device, and FIG. 2 shows the arrangement of conventional electrode pads as viewed from the chip surface. Semiconductor substrate 1 including one circuit cable as shown in FIG.
A placement conductor 3 is formed on the wiring conductor 3 via a first insulating film 2, and a second insulating film 4, that is, a chip passivation film is further formed on the wiring conductor 3. Next, an opening 5 is formed in the chip passivation plate 4 by ordinary photoresist processing and chemical etching, and then Ti6 and Cu7 are deposited on the entire surface in this order to a predetermined thickness.
ここで絶縁膜２としては熱酸化法やスノくツタリング法
、もしくは気相成長法（ＣＶＤ法）によって形成さ扛る
ＳｉＯ□、またはＣＶＤ法やスノ（ツタリング法によっ
て形成されるＡｌ２Ｏ３フォスフオシリケードガラス（
リンガラス）などが用いられる。一方、配線導体３とし
てはＡｊ！、Ｍｏ。Here, the insulating film 2 is SiO□ formed by a thermal oxidation method, a solar oxidation method, or a vapor phase growth method (CVD method), or an Al2O3 phosphor silicade formed by a CVD method or a solar oxidation method. Glass (
phosphorus glass) etc. are used. On the other hand, as the wiring conductor 3, Aj! , Mo.
：Ｐｔ、Ｔｉ、Ｃｒなどが用いらｎる。また該配線導体
３上の絶縁膜４すなわちチップ・シツシベーショノ膜と
しては前記スパッタリング法によるＳｉＯ２やリンガラ
スなどが用いらｆる。:Pt, Ti, Cr, etc. are used. Further, as the insulating film 4, that is, the chip insulation film on the wiring conductor 3, SiO2, phosphor glass, or the like formed by the sputtering method is used.
次に第１図（ｂｌに示すように、前記２層膜からなる配
線導体６．７上に再度ホトレジ処理全行ない。Next, as shown in FIG. 1 (bl), the entire wiring conductor 6.7 made of the two-layer film is again subjected to photoresist processing.
電極パッド形成位置８のみを開孔したホトレジスト膜９
を形成する。そして同図（Ｃ）に示す如（Ｎ ｉｌｏ、
５ｎ１１．Ｐｂ１２の順にメッキ法によってそ扛ぞれ所
定厚さだけ被着し、電極を形成する。Photoresist film 9 with holes only at electrode pad formation positions 8
form. And as shown in the same figure (C) (N ilo,
5n11. Pb12 is then deposited to a predetermined thickness by plating to form an electrode.
この後同図（ｄＪに示すように最初に該ホトレジスト膜
９を除去し、次に該Ｎｉ１ｎ、５ｎｌｌ、Ｐｂ１２から
なる電極パッドをマスクとしてｔ極部以外の前記２層ｊ
換の配線導体をＣｕ７ 、Ｔｉ６の順にそれぞｎ化学エ
ツチングする０最後に第１図（ｅ）に示すように約３５
０°Ｑ、１０分の熱処理によってハンダの突起電極１３
の形成を完了する。以上が従来のノ・ンダ電極の形成方
法である。After this, as shown in the same figure (dJ), the photoresist film 9 is first removed, and then the two layers other than the t-pole are removed using the electrode pads made of Ni1n, 5nll, and Pb12 as a mask.
The replacement wiring conductors are chemically etched in the order of Cu7 and Ti6.Finally, as shown in Figure 1(e), about 35mm
The solder protruding electrode 13 is heated at 0°Q for 10 minutes.
Complete the formation of. The above is the conventional method for forming a conductor electrode.
このようなハンダ電極は従来、第２図に七扛が１８個の
場合の−り１］を示すように、チップ内の能動索子領域
１４を（ｄすしてチップの周辺に配置されている。この
ため従来はハンダ電極１３の配置領域がチップ上（２）
においておよそ２０〜３０φを占めている。したがって
このノ・ンダ′這ｆｆ１１３を先の第１図に示したチッ
プバッシベーンヨン膜４を介して第２図に示す能動素子
領域１４上に設置するならは、チップ面積をそｎたけ縮
小することが可能となる。しかし、従来のチップパッシ
ベーション膜には耐クラツク性の点で次のような問題が
あった。すなわち本半導体装置の実装法であるＣＣＤ法
（Ｃｏｎｔｒｏｌｌｅｄ ＣＣｏ１１ａｐｓｅＢｏｎｄ
ｉｎ ）の接合において、そのときの熱処理（約３５
０℃、１０分）で膜の割ｔが生ずることである。このよ
うなりラックは先の第１図ｔｅｌで示したハンダの突起
電極形成においても生ずる。Conventionally, such solder electrodes are arranged around the periphery of the chip by extending the active wire area 14 in the chip (1) as shown in FIG. .For this reason, conventionally the placement area of the solder electrode 13 is on the chip (2).
occupies approximately 20 to 30φ. Therefore, if this non-enda' FF 113 is installed on the active element region 14 shown in FIG. 2 via the chip bass vane film 4 shown in FIG. 1, the chip area will be reduced by that amount. becomes possible. However, conventional chip passivation films have the following problems in terms of crack resistance. That is, the CCD method (Controlled CCo11apseBond) which is the mounting method of this semiconductor device is used.
in), the heat treatment at that time (approximately 35
0° C. for 10 minutes), the film cracks. Such a rack also occurs in the solder protrusion electrode formation shown in FIG. 1 above.
一方、このような電極配置においては１本装置金先のＣ
ＣＤ法によっては実装基板に装置した後、各電極に加わ
る各種ストレス、とりわけ熱的ストレスが不・均一とな
る。したがってたとえば電気的導通不良となるハンダ電
極にはチップ内の配置場所依存性が生ずるという欠点が
あった。On the other hand, in such an electrode arrangement, C
Depending on the CD method, various types of stress, especially thermal stress, applied to each electrode after the device is mounted on a mounting board may be non-uniform. Therefore, there is a drawback that, for example, the solder electrode, which causes poor electrical conduction, is dependent on the placement location within the chip.
そこで本発明は上述した従来装置の欠点を一挙に解決す
る半導体装置を提供するものである。第３図に本発明に
よる半導体装置の配線導体およびハンダ電極の形成方法
を示す。また第４図に本発明による磁極パッドの配置レ
イアウトの一例（ここでは１８個の電極パッドの場合）
を示す。Therefore, the present invention provides a semiconductor device that solves all of the above-mentioned drawbacks of the conventional devices. FIG. 3 shows a method for forming wiring conductors and solder electrodes of a semiconductor device according to the present invention. Furthermore, FIG. 4 shows an example of the arrangement layout of the magnetic pole pads according to the present invention (here, in the case of 18 electrode pads).
shows.
以下１本発明の詳細について述べる。The details of the present invention will be described below.
まず第３図（ａ）に示した構造が従来装置と著しく異な
る特徴は、図中のチップパッシベーション膜３４として
プラズマ放電中で膜生成を行なうプラズマＣＶＤ１化シ
リコン（以下Ｐ−８ｉＮという）を用いることである。First, the structure shown in FIG. 3(a) is significantly different from the conventional device in that plasma CVD silicon nitride (hereinafter referred to as P-8iN), which is formed during plasma discharge, is used as the chip passivation film 34 in the figure. It is.
こ牡は従来のスノくツタリング法によって形成さ扛る５
ｉｎ２やＣＶＤ法によって形成さｎるリンガラスに比べ
、本発明におけるＳｉＮが単位暎厚当りの機械的強度に
おいてそれぞｎ約１５倍、２５倍と耐クラツク性に優牡
ていることによる。なお同図（ａＪにおいて回路素子を
含む半導体基板３１上の第１の絶縁膜３２および配線導
体３３．そして−極パッドに至る、該チップパッシベー
ション膜３４上の２層膜の配線導体３６．３７はそｎぞ
れ従来装置と同一である。だだＬ４−ｙ−ップバッシベ
ーシヲンの開孔３５は通常のホトレジ処理そしてＣＦ４
ガスなどによるドライエツチングによって行なうとよ
い。次に第３図に示すように該２層膜の配線導体上に再
度ｐ−８ｉＮ３８を全面的に被着し、前述のホトレジ処
理、ドライエツチングによってその）くターニングを完
了し後述する２層膜の配線導体と同様の・くターントス
る。この後再度ホトレジ処理を行ナイ、電極パッド形成
位置３９のみを開孔したホトレジスト膜４０を形成する
。The oysters are formed by the traditional snow vine ringing method.5
This is because the SiN of the present invention has superior crack resistance, about 15 times and 25 times the mechanical strength per unit thickness, respectively, compared to phosphor glass formed by in2 and CVD methods. In the same figure (aJ), the first insulating film 32 and the wiring conductor 33 on the semiconductor substrate 31 including the circuit elements, and the wiring conductor 36 and 37 of the two-layer film on the chip passivation film 34 leading to the - pole pad are as shown in FIG. Each of them is the same as the conventional device.The aperture 35 of the L4-y-p bassy base is processed by normal photoresist processing and by CF4.
It is preferable to perform dry etching using gas or the like. Next, as shown in FIG. 3, p-8iN38 is again deposited on the entire surface of the wiring conductor of the two-layer film, and the turning process is completed by the photoresist process and dry etching described above, and the two-layer film is coated as described below. Toss the wiring conductor in a similar way. Thereafter, photoresist processing is performed again to form a photoresist film 40 with holes only at electrode pad forming positions 39.
ここで前記Ｐ −Ｓ ｉ Ｎ ３８は先の２層膜の配線
４体のパターンニング用マスクとして、また後述するハ
ンダの濡肛防止として用いるものである。Here, the P-S i N 38 is used as a mask for patterning the four wirings of the two-layer film described above, and also as a prevention of solder wetting, which will be described later.
したがってこの場合、ここではＰ−８ｉＮを用いている
が、たとえばＣｒ 、Ｔｉ 、ポリイミド樹月旨５ｉｎ
２など双方のプロセス条件を満足するものであれば他材
料でもよいことはいうまでもない。Therefore, in this case, P-8iN is used here, but for example, Cr, Ti, polyimide 5in
It goes without saying that other materials such as 2 may be used as long as they satisfy both process conditions.
次に第３図（ｃｌに示すように従来と同様Ｎ１４１Ｓｎ
４２ 、Ｐｂ４３の順にメッキ法によってそｎぞれ所定
の厚さだけ被着する。そして同図ｉｄ）に示したように
最初に該ホトレジスト膜４０を除去し。Next, as shown in Figure 3 (cl), the N141Sn
Pb42 and Pb43 are deposited to a predetermined thickness by plating in this order. Then, as shown in FIG. id), the photoresist film 40 is first removed.
次べ咳Ｐ−８ｉＮ３８をマスクとして前記２層膜の配線
導体をＣｕ３７ 、Ｔｉ３６の順に化学エツチングする
。この後第３図ｔｅｌのように約３５０°０１０分の熱
処理によってハンダ突起電極４４を形成する。このとき
前記Ｐ−ＳｉＮ３８はハンダが前記Ｃｕ３７の全面に濡
れることを防止する役目を担うことになる。Next, using P-8iN 38 as a mask, the wiring conductor of the two-layer film is chemically etched in order of Cu 37 and Ti 36. Thereafter, as shown in FIG. 3, solder protrusion electrodes 44 are formed by heat treatment for about 350° 010 minutes. At this time, the P-SiN 38 plays the role of preventing the solder from getting wet on the entire surface of the Cu 37.
上述したような本発明の半導体装置に８いて、次の特徴
は第４図に一例を示すように、電極パッドの配置レイア
ウトに関するものである。すなわち同図に示したように
前記ハンダ電極４４をチップ内の能動索子領域４５上面
に円状に配置したことである。この場合、ハンダ電極４
４を１つ以上の円周上に配置した、すなわち同心円状配
置でもよい。同図に示すように本発明においては該ハン
ダ電極４４を素子領域上面に設置するため、従来の電極
配置領域の面積たけチップ稲小が可能となる。一方ハン
ダ′電極を円状、あるいは同心円状に配−するため、従
来装置の欠点すなわち不良電極のチップ内湯所依存性を
なくすという大きな長所をもたらすこととなる。The next feature of the semiconductor device of the present invention as described above relates to the arrangement layout of the electrode pads, as shown in FIG. That is, as shown in the figure, the solder electrodes 44 are arranged in a circular shape on the upper surface of the active cable region 45 within the chip. In this case, solder electrode 4
4 may be arranged on one or more circumferences, that is, they may be arranged concentrically. As shown in the figure, in the present invention, since the solder electrode 44 is placed on the upper surface of the element area, it is possible to make the chip size smaller than the area of the conventional electrode arrangement area. On the other hand, since the solder electrodes are arranged circularly or concentrically, this device has the great advantage of eliminating the disadvantage of conventional devices, that is, the dependence of defective electrodes on the hot spots within the chip.
このように不発明による半導体装置は、ハンダ電極を・
耐クラツク性に優扛たＰ−８ｉＮ膜を介してＩＣチップ
の能動素子上面に円状、あるいは同心円状に配置した構
造を有するため、チップ面積の稲小ならびに実装後のハ
ンダ電極の接合部の信頼性向上に極めて貢献するもので
ある。In this way, the uninvented semiconductor device uses solder electrodes.
It has a structure in which the active elements of the IC chip are arranged circularly or concentrically on the top surface of the IC chip through a P-8iN film with excellent crack resistance, which reduces the chip area and reduces the solder electrode joints after mounting. This greatly contributes to improving reliability.
第１図ｔａ＞〜ｌｅ）は従来のノ・ンダ突起電極を有す
る半導体装置の製造工程を示す断面図、第２図は従来の
半導体装置におけるノ・ンダ突起電極の配置を示す平面
図、第３図（ＥＬ１〜（ｅ）は本発明の一実施例におけ
るハンダ突起磁極を有する半導体装置の製造工程を示す
断面図、第４図は本発明の一実施例における半導体装置
の・・ンダ突起電極の配置を示す平面図である。
１・・・半導体基板、２・・・第１の絶縁膜、３・・・
配線導体、４・・・第２の絶縁［（チップパッシベーシ
ョン映）、５・・・開孔、６・・・′ｒｉ、７・・・Ｃ
ｕ、８・・′成極パッド形成位置、９・・・ホトレジス
ト膜、１ＯＮｉ、１１−８ｎ、１２ 、・Ｐ ｂ、１３
・＝ノ／ダ突起電極、１４・・能動素子領域、３１・
・・半導体基板、３２・・・第１の絶縁膜、３３・・配
線導体、３４・・・テックハ、シベーシ田ンｆＡ（窒化
シリコン映）。
３５ ＝・開孔、３６ ・・Ｔ ｉ、３７−Ｃｕ、
３８−・・窒化シリコン、３９・・・電極パッド形成位
置、４０ ・ホトレジスト膜、４１・・・Ｎｉ、４２・
・・Ｓｎ、４３・・・ｐｂ、４４・・・・・ンダ突起電
極、４５・・・能動素子上面。
第１図
第 ２ 圓
第 ３ 田
第４図
第１頁の続き
０発 明 者 吉川育生
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 大路譲
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 平岩篤
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内Figures 1(a) to 1(e) are cross-sectional views showing the manufacturing process of a conventional semiconductor device having a protruding electrode, FIG. 2 is a plan view showing the arrangement of protruding electrodes in a conventional semiconductor device, and FIG. 3 (EL1 to EL1-(e) are cross-sectional views showing the manufacturing process of a semiconductor device having a solder protrusion magnetic pole in an embodiment of the present invention, and FIG. 4 is a sectional view showing a solder protrusion electrode of a semiconductor device in an embodiment of the present invention. 1 is a plan view showing the arrangement of 1... semiconductor substrate, 2... first insulating film, 3...
Wiring conductor, 4... Second insulation [(chip passivation reflection), 5... Opening, 6...'ri, 7... C
u, 8...' Polarization pad formation position, 9... Photoresist film, 1ONi, 11-8n, 12, ・P b, 13
・=No/da protruding electrode, 14. Active element area, 31.
. . . Semiconductor substrate, 32 . . . First insulating film, 33 . . Wiring conductor, 34 . . . 35 = Open hole, 36...T i, 37-Cu,
38--Silicon nitride, 39--Electrode pad formation position, 40-Photoresist film, 41--Ni, 42-
. . . Sn, 43 . . . pb, 44 . . . conductor protrusion electrode, 45 . Figure 1 Figure 2 Round 3 Figure 4 Continued from page 1 0 Author: Ikuo Yoshikawa 1-280 Higashi Koigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory 0 Author: Yuzuru Oji 1-280 Higashi Koigakubo, Kokubunji City Inside the Central Research Laboratory, Hitachi, Ltd. 0 Inventor: Atsushi Hiraiwa, 1-280 Higashikoigakubo, Kokubunji City, Inside the Central Research Laboratory, Hitachi, Ltd.
Claims (1)
所定の第１の開口部を有する第１の絶縁膜、該第１の開
口部を介して該半導体基板に接続し且つ該第１の絶縁膜
上に延在する配線導体、該第１の絶縁膜および該配線導
体を被覆し且つ所定の第２の開口部を有する。プラズマ
放電中で形成された窒化シリコン膜、該第２の開口部を
介して該配線導体に接続し且つ該窒化シリコン膜上に延
在する２層膜の配線導体、該２層膜の配線導体の所定位
置上に設けらｎたハンダ突起電極、および第２層膜の配
線導体の該ハンダ突起電極によシ被覆されていない表面
に設けられハンダとの濡れ性の低い被覆層を有し、且つ
該ハンダ突起電極が円状もしくは同心円状に配置されて
いることを特徴とする半導体装置。1. A first insulating film having a predetermined first opening on a semiconductor substrate having at least one circuit element, the first insulating film being connected to the semiconductor substrate through the first opening; A wiring conductor extending on the film, covering the first insulating film and the wiring conductor, and having a predetermined second opening. A silicon nitride film formed during plasma discharge, a wiring conductor of a two-layer film connected to the wiring conductor through the second opening and extending over the silicon nitride film, and a wiring conductor of the two-layer film. a solder protrusion electrode provided on a predetermined position, and a coating layer with low wettability with solder provided on the surface of the wiring conductor of the second layer film that is not covered by the solder protrusion electrode, A semiconductor device characterized in that the solder protrusion electrodes are arranged circularly or concentrically.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59027045A JPS59161051A (en) | 1984-02-17 | 1984-02-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59027045A JPS59161051A (en) | 1984-02-17 | 1984-02-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161051A true JPS59161051A (en) | 1984-09-11 |
Family
ID=12210100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59027045A Pending JPS59161051A (en) | 1984-02-17 | 1984-02-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161051A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196409A (en) * | 2000-01-03 | 2001-07-19 | Motorola Inc | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940383A (en) * | 1972-08-24 | 1974-04-15 | ||
| JPS4991767A (en) * | 1972-12-26 | 1974-09-02 |
-
1984
- 1984-02-17 JP JP59027045A patent/JPS59161051A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940383A (en) * | 1972-08-24 | 1974-04-15 | ||
| JPS4991767A (en) * | 1972-12-26 | 1974-09-02 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196409A (en) * | 2000-01-03 | 2001-07-19 | Motorola Inc | Semiconductor device |
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