JPH0638417B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0638417B2 JPH0638417B2 JP62252841A JP25284187A JPH0638417B2 JP H0638417 B2 JPH0638417 B2 JP H0638417B2 JP 62252841 A JP62252841 A JP 62252841A JP 25284187 A JP25284187 A JP 25284187A JP H0638417 B2 JPH0638417 B2 JP H0638417B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- outer peripheral
- peripheral portion
- lead
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、ワイヤレスボンディング方式に用いる半導体
装置に係わり、特にバンプ電極を用いた電極引き出し部
の形成の改良に関する。The present invention relates to a semiconductor device used in a wireless bonding method, and more particularly to an improvement in formation of an electrode lead portion using a bump electrode.
（従来の技術） 従来の半導体装置のバンプ形成工程とバンプとリードと
の接合工程とについて第２図を参照して以下に説明す
る。第２図(a)において、拡散済みのSi基板１上にSiO2
膜２が形成され、その上に配線パターンと接続している
Ａ電極パッド３が形成されている。Ａ電極パッド３
の上の部分を開孔した保護用のSi３Ｎ４膜４が半導体素
子上の全面に被覆されている。まずこの基板の全面に真
空蒸着法により1000〜2000Å厚のTi層を形成し、その上
に連続して1000〜2000ÅのPd層を蒸着し、Pd/Tiの２層
金属膜５を形成する。(Prior Art) A conventional bump forming process of a semiconductor device and a bonding process of a bump and a lead will be described below with reference to FIG. In FIG. 2 (a), SiO 2 is deposited on the diffused Si substrate 1.
The film 2 is formed, and the A electrode pad 3 connected to the wiring pattern is formed thereon. A electrode pad 3
A protective Si 3 N 4 film 4 having a hole formed on the upper part of the substrate is covered on the entire surface of the semiconductor element. First, a Ti layer having a thickness of 1000 to 2000Å is formed on the entire surface of this substrate by a vacuum evaporation method, and a Pd layer having a thickness of 1000 to 2000Å is continuously vapor-deposited thereon to form a Pd / Ti two-layer metal film 5.
次に同図(b)において、液状ホトレジスト６をスピンナ
ー塗布（約1.2μｍ厚）し、電極パッド３の上部にの
み、所望の大きさのバンプ径をパターニング開孔する。
同図(c)において、このホトレジスト６をメッキマスク
とし、前記Pd/Ti金属膜５を電解メッキの一方の電極
（この場合には陰極）として、電極パッド上部にのみ選
択的にAu７を析出させる。次同図(d)においてホトレジ
ストの除去を行い、析出させたAu７をマスクにして、電
極パッド上部以外のPd/Ti金属膜５を硝酸、塩酸、酢酸
の混酸でエッチング除去する。このようにしてＡ電極
パッド３上部に、Au-A相互拡散抑制層（バリヤ層とも
呼ばれる）のPd/Ti金属膜５を介してAuバンプ７を形成
する。また必要な場合には金属各層の接触抵抗の低減を
目的とする約３８０℃のＮ２雰囲気中の熱処理を行う。Next, in FIG. 3B, a liquid photoresist 6 is applied by spinner (thickness of about 1.2 μm), and a bump diameter of a desired size is patterned and opened only on the upper portion of the electrode pad 3.
In FIG. 3C, the photoresist 6 is used as a plating mask, and the Pd / Ti metal film 5 is used as one electrode (cathode in this case) of electrolytic plating to selectively deposit Au 7 only on the upper portion of the electrode pad. . Next, in FIG. 3D, the photoresist is removed, and the deposited Au 7 is used as a mask to etch away the Pd / Ti metal film 5 other than the upper part of the electrode pad with a mixed acid of nitric acid, hydrochloric acid and acetic acid. Thus, the Au bumps 7 are formed on the A electrode pads 3 with the Pd / Ti metal film 5 of the Au-A interdiffusion suppressing layer (also called a barrier layer) interposed therebetween. If necessary, heat treatment is performed in an N 2 atmosphere at about 380 ° C. for the purpose of reducing the contact resistance of each metal layer.
次にリード８との接合はボンディングツール９により、
ツール表面温度約３５０℃、素子加熱約２７０℃、ツー
ル加圧約５０ｇ／バンプ程度の条件で、Cuリード表面に
約0.4μｍ厚でメッキされているSnとAuバンプとの共晶
合金形成による接合を行う。Next, the bonding with the lead 8 is performed by the bonding tool 9.
Under the conditions of tool surface temperature of about 350 ° C, element heating of about 270 ° C, tool pressure of about 50 g / bump, bonding of Sn and Au bumps plated on the Cu lead surface with a thickness of about 0.4 μm by forming a eutectic alloy. To do.
（発明が解決しようとする問題点） 上述した従来技術によれば、近年の高集積化の進むＬＳ
Ｉに対してＴＡＢ(Tape Automated Bonding)法を用いる
場合、ＴＡＢ法自身の問題点として、信号入出力端子を
半導体チップの外周から外部へ引き出さなければならな
いため、ボンディング可能な電極数に限界がある。バン
プ形成可能な最小パッドピッチ（〜８０μｍ）とリード
加工精度の相乗効果により接合可能最大電極数は試算上
１０mm角チップに対して５００とされている。（例え
ば、日本金属学会会報23(1984),1005頁）現状では、ゲ
ートアレイの多ピン化対応のＴＡＢ化、スーパーインテ
グレーションＬＳＩのＴＡＢ化は極めて困難な状況にあ
る。また、パッド数の増大により、内部素子領域外の面
積が増大し、素子の高集積化に比してチップ内の非活性
領域が増大するといった不経済が生じることになる。(Problems to be Solved by the Invention) According to the above-described conventional technology, LS having a high degree of integration in recent years has advanced.
When the TAB (Tape Automated Bonding) method is used for I, the problem with the TAB method itself is that the number of electrodes that can be bonded is limited because the signal input / output terminals must be pulled out from the outer periphery of the semiconductor chip. . Due to the synergistic effect of the minimum pad pitch (up to 80 μm) capable of forming bumps and the lead processing accuracy, the maximum number of electrodes that can be bonded is set to 500 for a 10 mm square chip. (For example, Japan Institute of Metals, Proceedings 23 (1984), p. 1005) At present, it is extremely difficult to make a TAB for a multi-pin gate array and a TAB for a super integration LSI. In addition, the increase in the number of pads causes an increase in the area outside the internal element region, resulting in an uneconomical increase in the inactive region in the chip as compared with the high integration of the device.
本発明の目的は、高さの異なるバンプ電極列を素子内外
周部に並列に配置し、これに対応したテープキャリヤ上
のリードとの多点一括接合を可能とする半導体装置を提
供することにある。It is an object of the present invention to provide a semiconductor device in which bump electrode arrays having different heights are arranged in parallel on the inner and outer peripheral parts of the element, and corresponding multi-point collective bonding with leads on a tape carrier is possible. is there.
［発明の構成］ （問題点を解決するための手段と作用） 本発明は、半導体素子の信号入出力電極として、バンプ
と称する金属突起電極（バンプ電極という）を電極パッ
ド上に有する半導体装置において、集積回路が形成され
た半導体基板上に設けられる電極パッドを、前記半導体
基板の内部素子領域上の第１の外周部とこれより外側に
ある第２外周部として配置せしめ、前記第１外周部の電
極パッド上に形成されるバンプ電極の高さを第２外周部
のそれより高くしたことを第１の特徴とする。また、半
導体素子の信号入出力電極として、バンプと称する金属
突起電極（バンプ電極という）を電極パッド上に有する
半導体装置において、集積回路が形成された半導体基板
上に設けられる電極パッドを、前記半導体基板の内部素
子領域上の第１外周部とこれより外側にある第２外周部
として配置せしめ、前記第１外周部の電極パッド上に形
成されるバンプ電極の高さを第２外周部のそれより高く
した半導体装置を設け、前記第１外周部と第２外周部に
位置する電極パッド上に形成されたバンプ電極に対し
て、両者の高さの差に等しい段差を有する多層のリード
を具備するフィルムキャリヤテープにより、一括同時に
各バンプ電極とリードとの接合を行なうことを第２の特
徴とする。即ち本発明は、バンプ形成時のメッキマスク
として厚膜感光性樹脂を用い、開口部の面積を変化させ
ることにより、同一素子内で高さの異なるバンプ電極を
形成し、絶縁樹脂層を介在させ多層に形成されたリード
を用いることにより、ＴＡＢ法の接合可能電極数を飛躍
的に増大させようとするものである。[Configuration of the Invention] (Means and Actions for Solving Problems) The present invention relates to a semiconductor device having metal bump electrodes called bumps (called bump electrodes) on electrode pads as signal input / output electrodes of a semiconductor element. The electrode pads provided on the semiconductor substrate on which the integrated circuit is formed are arranged as a first outer peripheral portion on the internal element region of the semiconductor substrate and a second outer peripheral portion outside the first outer peripheral portion, and the first outer peripheral portion is provided. The first feature is that the height of the bump electrode formed on the electrode pad is higher than that of the second outer peripheral portion. In a semiconductor device having metal bump electrodes called bumps (called bump electrodes) on electrode pads as signal input / output electrodes of a semiconductor element, the electrode pads provided on a semiconductor substrate on which an integrated circuit is formed are The bumps formed on the electrode pads of the first outer peripheral portion are arranged as the first outer peripheral portion and the second outer peripheral portion on the inner element region of the substrate, and the height of the bump electrode formed on the electrode pad of the first outer peripheral portion is set to that of the second outer peripheral portion. A semiconductor device having a higher height is provided, and a multilayer lead having a step equal to the height difference between the bump electrodes formed on the electrode pads located at the first outer periphery and the second outer periphery is provided. The second feature is that the bump electrodes and the leads are simultaneously joined at once by the film carrier tape. That is, according to the present invention, a thick film photosensitive resin is used as a plating mask when forming bumps, and by changing the area of the opening, bump electrodes having different heights are formed in the same element, and an insulating resin layer is interposed. By using leads formed in multiple layers, the number of electrodes that can be joined by the TAB method is dramatically increased.
（実施例） 第１図は本発明の半導体装置の１つの実施例を示す製造
工程図である。まず、半導体素子が形成された図１(a)
のような配置の電極パッド上に所定の開口部を有する絶
縁保護膜１２（例えば、プラズマＣＶＤ法による窒化シ
リコン膜など）が堆積済みである半導体基板１１に対し
て真空蒸着法又はスパッタリング法によるり例えばTi−
Ｗ合金、又はPd/Tiなどの金属薄膜層１３を数千オング
ストロームの膜厚で全面に形成する。次に、例えばドラ
イフィルムレジストの様な厚膜感光性樹脂膜１４（２０
〜３０μｍ厚）を全面に被着する。引き続くホトリソグ
ラフィ工程において、電極パッド上のバンプ電極形成予
定領域のみ開口部を形成するが、この時、半導体装置の
内部素子領域の第１外周部の開口部１５が第２外周部の
開口部１６より小さくなるように設定する。次に第１図
(b)，(c)のように前記金属薄膜層１３を電解メッキの陰
極として、電極パッド上部の開口部にのみ選択的にAuを
電解析出させる。最後に、前記マスクとなった厚膜感光
性樹脂膜を剥離して完全に除去し、析出させたAuバンプ
電極１７，１８自身をマスクとして、電極パッド以外の
領域上に形成されている金属薄膜層１３をエッチング除
去し、Auバンプ電極１７，１８が形成される。(Embodiment) FIG. 1 is a manufacturing process chart showing one embodiment of a semiconductor device of the present invention. First, a semiconductor element is formed as shown in FIG.
A semiconductor substrate 11 on which an insulating protective film 12 (for example, a silicon nitride film formed by a plasma CVD method) having a predetermined opening has been deposited on the electrode pad arranged as above is formed by a vacuum evaporation method or a sputtering method. For example Ti-
A metal thin film layer 13 of W alloy or Pd / Ti is formed on the entire surface with a film thickness of several thousand angstroms. Next, for example, a thick photosensitive resin film 14 (20) such as a dry film resist is used.
˜30 μm thick) is applied over the entire surface. In the subsequent photolithography process, the opening is formed only in the region where the bump electrode is to be formed on the electrode pad. At this time, the opening 15 in the first outer peripheral portion and the opening 16 in the second outer peripheral portion of the internal element region of the semiconductor device are formed. Set it to be smaller. Next, Fig. 1
As in (b) and (c), the metal thin film layer 13 is used as a cathode for electrolytic plating, and Au is selectively electrolytically deposited only in the opening above the electrode pad. Finally, the thick photosensitive resin film used as the mask is peeled and completely removed, and the deposited Au bump electrodes 17 and 18 are used as a mask to form a metal thin film formed on a region other than the electrode pad. The layer 13 is removed by etching, and Au bump electrodes 17 and 18 are formed.
従来、メッキマスクとして、スピンコートによるフォト
レジスト（約１〜２μｍ厚）が使用されていたが、Auメ
ッキ析出に対してレジスト厚を越えた時点から以降のメ
ッキ横方向成長によりキノコ状のバンプ電極となり、形
状制御が極めて困難であった。本実施例で示すように、
ドライフィルムレジストの様な厚膜樹脂膜をメッキレジ
ストとして使用した場合、バンプ電極形状は柱状にな
り、従ってメッキ条件が一定の場合、すなわち電流密
度、メッキ時間が一定の条件の下では、 「（析出量）∝（面積）×（高さ）」となり、形状制御
が極めて容易になる。本実施例では、第１外周部のAuバ
ンプ形状が60μｍ×60μｍ×25μｍ（高さ）、第２外周
部では80μｍ×80μｍ×14μｍ（高さ）となり、両者共
に例えば４インチウェーハ内バラツキで±1.5μｍを確
保できている。Conventionally, a photoresist (about 1 to 2 μm thick) by spin coating has been used as a plating mask. However, from the time when the resist thickness is exceeded for Au plating deposition, the mushroom-shaped bump electrode is formed due to lateral plating growth thereafter. Therefore, the shape control was extremely difficult. As shown in this example,
When a thick resin film such as a dry film resist is used as the plating resist, the bump electrode shape becomes columnar. Therefore, when the plating conditions are constant, that is, when the current density and the plating time are constant, “( Deposition amount) ∝ (area) x (height) ", and shape control becomes extremely easy. In the present embodiment, the Au bump shape of the first outer peripheral portion is 60 μm × 60 μm × 25 μm (height), and the second outer peripheral portion is 80 μm × 80 μm × 14 μm (height). 1.5 μm can be secured.
次に、上記の電極パッド配置、第１，第２外周部に形成
されるバンプ高さを考慮し、図１(c)，(d)に示す２層構
造のリード１９１，１９２を有するフィルムキャリヤテ
ープ１９を形成すればよい。これは、通常のポリイミド
基材上のエッチングによるCuリードパターン形成と表面
Snメッキを２回行なうことにより容易に形成できる。Next, in consideration of the above electrode pad arrangement and the bump heights formed on the first and second outer peripheral portions, the leads 19 1 and 19 2 having a two-layer structure shown in FIGS. 1C and 1D are provided. The film carrier tape 19 may be formed. This is Cu lead pattern formation and surface by etching on a normal polyimide substrate.
It can be easily formed by performing Sn plating twice.
更に、バンプ電極とリードの接合は、図１(d)に示すよ
うなボンディングツール２０により、全点同時一括接合
が可能となる。又は、第１外周部は通常のインナーリー
ドボンディングツール、第２外周部はアウターリードボ
ンディングツールを用いてもよい。第２外周部のAuバン
プとリードの熱圧着接合は、ポリイミド層を介しての接
合部への加熱となるが、通常ツール温度４００℃，ボン
ディング時間１秒程度のボンディングであれば、第１外
周部と同様な接合条件下にあると考えてよい。Further, the bump electrode and the lead can be bonded simultaneously at all points by using the bonding tool 20 as shown in FIG. 1 (d). Alternatively, a normal inner lead bonding tool may be used for the first outer peripheral portion and an outer lead bonding tool may be used for the second outer peripheral portion. The thermocompression bonding of the Au bump and the lead on the second outer periphery is heating to the bonding portion via the polyimide layer, but if the bonding is performed at a tool temperature of 400 ° C. and a bonding time of about 1 second, the first outer periphery is used. It may be considered that they are under the same joining conditions as the parts.
［発明の効果］ 以上説明したように本発明によれば、従来のＴＡＢ法が
半導体チップの外周１列に配置された電極パッド上に形
成されたバンプ電極からのみ信号入出力端子を引き出せ
なかったが、本発明によるバンプ電極形成とリード接合
工程により、外周並列の電極パッド配置によるＴＡＢ化
を可能とし、飛躍的な電極接続数の増大、同一パッド数
に対して、内部素子領域外面積の大幅な縮小によるチッ
プサイズ自身の縮小を可能とし、ボードアッセンブリコ
ストの低減、回路システムにおいては、高密度実装によ
る配線長の短縮化による機能向上を計ることができる。As described above, according to the present invention, the conventional TAB method cannot extract the signal input / output terminal only from the bump electrode formed on the electrode pad arranged in the outer peripheral one row of the semiconductor chip. However, the bump electrode formation and the lead bonding process according to the present invention enables TAB by arranging electrode pads in parallel with the outer circumference, which dramatically increases the number of electrode connections and significantly reduces the area outside the internal element region with respect to the same number of pads. It is possible to reduce the chip size itself by reducing the size, reduce the board assembly cost, and in the circuit system, it is possible to improve the function by shortening the wiring length by high-density mounting.
第１図は本発明の実施例の製造工程を示す断面図で、同
図(c)のみは同図(b)のパターン平面図、第２図は従来技
術の製造工程を示す断面図である。 １１……半導体基板、１３……金属薄膜層、１４……メ
ッキマスク、１７，１８……Auバンプ、１９１，１９２
……リード、２０……ボンディングツール。FIG. 1 is a cross-sectional view showing a manufacturing process of an embodiment of the present invention, only FIG. 1C is a pattern plan view of FIG. 1B, and FIG. 2 is a cross-sectional view showing a conventional manufacturing process. . 11 ... Semiconductor substrate, 13 ... Metal thin film layer, 14 ... Plating mask, 17, 18 ... Au bump, 19 1 , 19 2
...... Lead, 20 …… bonding tool.
Claims (3)
部に形成される第１の電極パッドと、前記第１外周部よ
りも外側にある第２外周部に形成される第２の電極パッ
ドと、前記第１の電極パッド上に設けられる第１のバン
プと、前記第２の電極パッド上に設けられ、前記第１の
バンプよりも高さの低い第２のバンプと、前記第１のバ
ンプに接続される第１のリード及び前記第２のバンプに
接続される第２のリードを有し、前記第１のリードと前
記第２のリードの間隔は、前記第１のバンプと前記第２
のバンプの高さの差に概ね等しい絶縁基板とを備え、 前記第１のバンプの高さｈ１及び前記第２のバンプの高
さｈ２は、 Ｓ１×ｈ１＝Ｓ２×ｈ２＝一定 （但し、Ｓ１は、第１のバンプの底面積、Ｓ２は、第２
のバンプの底面積であり、Ｓ２＞Ｓ１を満たす。） の関係を有することを特徴とする半導体装置。1. A semiconductor substrate, a first electrode pad formed on a first outer peripheral portion of the semiconductor substrate, and a second electrode formed on a second outer peripheral portion outside the first outer peripheral portion. A pad, a first bump provided on the first electrode pad, a second bump provided on the second electrode pad and having a height lower than that of the first bump; A first lead connected to the first bump and a second lead connected to the second bump, and the distance between the first lead and the second lead is equal to the first bump and the second lead. Second
And a height h1 of the first bump and a height h2 of the second bump are: S1 × h1 = S2 × h2 = constant (where S1 Is the bottom area of the first bump, S2 is the second area
Is the bottom area of the bump and satisfies S2> S1. ) The semiconductor device having the following relationship.
つは、前記半導体基板の内部素子領域上に設けられてい
ることを特徴とする特許請求の範囲第１項に記載の半導
体装置。2. The semiconductor device according to claim 1, wherein at least one of the first and second bumps is provided on an internal element region of the semiconductor substrate.
ッドを形成すると共に前記第１外周部よりも外側にある
第２外周部に第２の電極パッドを形成する工程と、 前記半導体基板上に絶縁膜を形成する工程と、 前記第１の電極パッド上の絶縁膜に面積Ｓ１の開口部を
形成すると共に前記第２の電極パッド上の絶縁膜に面積
Ｓ２の開口部を形成する（但し、Ｓ２＞Ｓ１とする）工
程と、 電解メッキ法を用いて、前記絶縁膜をマスクにして、一
定条件下で前記第１及び第２の開口部に導電物を堆積さ
せ、面積Ｓ１の開口部に高さｈ１の第１のバンプを形成
すると共に面積Ｓ２の開口部に高さｈの第２のバンプを
形成する（但し、Ｓ１×ｈ１＝Ｓ２×ｈ２＝一定）工程
と、 前記絶縁膜を除去する工程と、 絶縁基板の第１のリードを前記第１のバンプに接続する
と共に前記絶縁基板の第２のリードを前記第２のバンプ
に接続する工程と を具備することを特徴とする半導体装置の製造方法。3. A step of forming a first electrode pad on a first outer peripheral portion on a semiconductor substrate and forming a second electrode pad on a second outer peripheral portion outside the first outer peripheral portion, Forming an insulating film on the semiconductor substrate, and forming an opening of area S1 in the insulating film on the first electrode pad and forming an opening of area S2 in the insulating film on the second electrode pad. (Provided that S2> S1), and using an electrolytic plating method, using the insulating film as a mask, depositing a conductive material in the first and second openings under certain conditions to obtain an area S1. Forming a first bump having a height h1 in the opening of the above, and forming a second bump having a height h in the opening having an area S2 (provided that S1 × h1 = S2 × h2 = constant), Removing the insulating film, and connecting the first lead of the insulating substrate to the first band. The method of manufacturing a semiconductor device characterized by comprising the step of connecting the second lead of the insulating substrate to the second bump while connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62252841A JPH0638417B2 (en) | 1987-10-07 | 1987-10-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62252841A JPH0638417B2 (en) | 1987-10-07 | 1987-10-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0195539A JPH0195539A (en) | 1989-04-13 |
| JPH0638417B2 true JPH0638417B2 (en) | 1994-05-18 |
Family
ID=17242930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62252841A Expired - Fee Related JPH0638417B2 (en) | 1987-10-07 | 1987-10-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0638417B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173763A (en) * | 1991-02-11 | 1992-12-22 | International Business Machines Corporation | Electronic packaging with varying height connectors |
| US5977618A (en) | 1992-07-24 | 1999-11-02 | Tessera, Inc. | Semiconductor connection components and methods with releasable lead support |
| US5915752A (en) | 1992-07-24 | 1999-06-29 | Tessera, Inc. | Method of making connections to a semiconductor chip assembly |
| US6239384B1 (en) | 1995-09-18 | 2001-05-29 | Tessera, Inc. | Microelectric lead structures with plural conductors |
| EP0956745A1 (en) * | 1995-09-18 | 1999-11-17 | Tessera, Inc. | Microelectronic lead structures with dielectric layers |
| KR100541649B1 (en) * | 2003-09-03 | 2006-01-11 | 삼성전자주식회사 | Tape circuit substrate and semiconductor chip package using thereof |
| JP2007329278A (en) * | 2006-06-07 | 2007-12-20 | Oki Electric Ind Co Ltd | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133877A (en) * | 1978-04-07 | 1979-10-17 | Nec Corp | Semiconductor device |
| JPS556868A (en) * | 1978-06-29 | 1980-01-18 | Nec Corp | Semiconductor device |
| JPS5787145A (en) * | 1980-11-20 | 1982-05-31 | Seiko Epson Corp | Semiconductor device |
-
1987
- 1987-10-07 JP JP62252841A patent/JPH0638417B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0195539A (en) | 1989-04-13 |
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