JPS59159560A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59159560A JPS59159560A JP58033439A JP3343983A JPS59159560A JP S59159560 A JPS59159560 A JP S59159560A JP 58033439 A JP58033439 A JP 58033439A JP 3343983 A JP3343983 A JP 3343983A JP S59159560 A JPS59159560 A JP S59159560A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- capacitor
- oxide film
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0777—Vertical bipolar transistor in combination with capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、ノ々イボーラ型半導体装置に係り、特にクロ
ストーク特性の良いリニアエＯＫ関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Nono Ibora semiconductor device, and particularly to a linear OK device with good crosstalk characteristics.
＋Ｊ ニアエＣは、入力信号をそのままの形で増幅して
出力する増幅器を基本としており、ＯＲ結合された増幅
器の段間には、信号成分のみを伝達し、不要な直流成分
を阻止するカップリングコンデンサが設けられるのが通
常である。+J Niae C is based on an amplifier that amplifies the input signal as it is and outputs it, and between the OR-coupled amplifier stages there is a coupling that transmits only the signal component and blocks unnecessary DC components. A capacitor is usually provided.
トランジスタ回路、におけるカップリングコンデンサは
周波数にもよるが、一般に大きな容量が必要であり、集
積化した半導体装置ではカップリングコンデンサはＭＯ
８構造をとることが多い。Coupling capacitors in transistor circuits generally require large capacitance, depending on the frequency, and in integrated semiconductor devices, coupling capacitors are MO
It often has an 8-structure.
これは、例えば第１図の断面図に示すようなものであっ
て、図示しないｐ型基板の上部にエピタキシャル成長等
によって作られたｎ型不純物を含むＤ型頭域／の表面部
にはｎ型不純物を高濃度に含むｎ＋領域コが形成され、
このｎ＋領域λの上部にコ酸化シリコン等による絶□縁
膜３が誘電体として形成されており、ｎ 領域ａからア
ルミニウム電極ケを介して引き出された端子ａと絶縁膜
３上に形成されたアルミニウム金属層５を介して引き出
された端子す間で容量を蓄えるものである。This is, for example, as shown in the cross-sectional view of FIG. An n+ region containing a high concentration of impurities is formed,
An insulating film 3 made of co-silicon oxide or the like is formed as a dielectric on the upper part of this n+ region λ, and a terminal a drawn out from the n+ region a via an aluminum electrode and formed on the insulating film 3 Capacity is stored between the terminals drawn out through the aluminum metal layer 5.
このよう゛なＭｏｓ構造のコンデンサは、従来トランジ
スタとけ別個のｌｌ型領域に形成され、アルミニウム配
線により所定の接続が行われている。Conventionally, such a Mos structure capacitor is formed in an ll-type region separate from the transistor, and is connected in a predetermined manner by aluminum wiring.
ところが、このような構造のコンデンサにおいては電極
ケからｎ＋領域ユを経て基板／Ｗ至るもう一つの寄生容
量Ｃが等測的に生ずる。この寄日
牛容量ＯＳは第Ω図の回路図中の点線に示すように入力
端子ａから直接基板のアースへ電流を流す回路を形成す
ることになり、この寄生容ｔｃ５が数ｐＦに達する事も
珍しくない。従って寄生容量の大きさはコンデンサの容
量値そのものに比１，７で無視できないものである。そ
してこの寄生容′Ｉｉによって信列が基板に漏れ、数Ｄ
Ｂないし／（）数ＤＢのクロストークを生じさせるとい
う問題がある。However, in a capacitor having such a structure, another parasitic capacitance C is generated isometrically from the electrode via the n+ region to the substrate/W. This parasitic capacitance OS forms a circuit that allows current to flow directly from the input terminal a to the ground of the board, as shown by the dotted line in the circuit diagram in Figure Ω, and this parasitic capacitance tc5 reaches several pF. It's not uncommon. Therefore, the size of the parasitic capacitance is a ratio of 1.7 to the capacitance value of the capacitor itself, and cannot be ignored. Then, due to this parasitic capacitance 'Ii, the signal train leaks to the substrate, and the number D
There is a problem that crosstalk of B to several DB occurs.
そこで、本発明はノζイポーラ型すニア丁Ｃにおけるカ
ップリングコンデンサの寄生容量によって生じるクロス
トークを減少させることを目的とする。Therefore, an object of the present invention is to reduce the crosstalk caused by the parasitic capacitance of the coupling capacitor in the non-ζ polar type sunar capacitor C.
上記目的達成のため、本発明においては酸化膜コンデン
サの導電領域としてｐ型領域を用い、これをエミッタフ
ォロアとし、て使用されるｎｐｎトジンジスタと共に同
一の分離領域により囲まれた同一のｎ型領域内に形成し
、酸化膜コンデンサのｐ型領域をｎｐｎ トランジスタ
のエミッタ領域に電気的に接続するようにしており、酸
化膜コンデンサの絡生容量を通じて基板側に電流が流れ
ない／ζめ、クロストークの発生を抑えることができる
ものである。In order to achieve the above object, in the present invention, a p-type region is used as the conductive region of the oxide film capacitor, and this is used as an emitter follower, and the same n-type region surrounded by the same isolation region is used together with the npn transistor used as the emitter follower. The p-type region of the oxide film capacitor is electrically connected to the emitter region of the npn transistor. It is possible to suppress the occurrence.
以下、第３図ないし第ｇ図を参照しながら本発明の実施
例のいくつかを説明する。１
第３図および第を図は本発明の基本的な実施例を示して
おり、第３図の平面図におけるＡ−Ａ’線に沼った断面
図が第４図である。Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 3 to g. 1. FIGS. 3 and 3 show a basic embodiment of the present invention, and FIG. 4 is a sectional view taken along line AA' in the plan view of FIG. 3.
これによれば、ｐ型基板／／上に形成されたｎ型領域／
−ｉはｐ＋分離（アイソレージ日／）領域／３によりて
囲まれており、いわゆる島を形成している。According to this, an n-type region formed on a p-type substrate//
-i is surrounded by a p+ isolation region /3, forming a so-called island.
とのｎ ｉｉ７頭城／、Ｉ内にはｎｐｎトランジスタの
（−スとなるｐ型領域／４７、コレクタとなるＩＩ ’
−領域／Ａ、コンデンツの導電領域となるｐ型領域／７
が形成され、ベースの１）型領域／ｌの中にはさらにエ
ミッタ領域となるｎ＋領領域形成されている５、１１つ
型領域／７の土部ＷけＪ酸化シリコン等による絶縁膜！
ｇが形成さ才１．さらにその上にはアルミニウム１層／
９が形成され′（いてこれらはＭ ＯＳ型のコンデンサ
な形成している。ｎ＋領域／３、ｐ種領域／夕、ｎ＋領
域／／、、ｐ ｆｉｉ！Ｉ領域１７にはそれぞれ電極、
２／ 、 ｊ、２ 、２．３゜、２０が形成されていて
、それぞれの領域からの引出ｊ７が行われている。なお
、エミッタ電極、２／とＭＯ３コンデンザ″ｖｆ、極２
０とはアルミニウム配線で直接接続されており、他の電
極も、図示されていないが、他の分＃された領域にある
回路構成要素と接続されており、基板上には集積回路が
形成されている。The p-type region /47 which becomes the (− source) of the npn transistor, and the collector II '
-Region/A, p-type region/7 which becomes the conductive region of the content
is formed, and in the 1) type region /l of the base, an n+ region which becomes an emitter region is further formed.
G is formed 1. Furthermore, there is one layer of aluminum on top of that.
9' (these form a MOS type capacitor. n+ region/3, p type region/2, n+ region//, p fii! I region 17 has electrodes, respectively.
2/, j, 2, 2.3°, and 20 are formed, and extraction j7 from each area is performed. In addition, emitter electrode, 2/ and MO3 capacitor "vf, pole 2
0 is directly connected with aluminum wiring, and other electrodes are also connected to circuit components in other divided areas (not shown), and an integrated circuit is formed on the substrate. ing.
このような構造の集積回路装置（は、公知の方法を用い
て例えば次のＪ″うに作ることができる６凍ず、ｐ型シ
リコン基板／／を準備し、この表面にｎ型不純物例虹げ
リンを反応ガスの中にＰ−ブしながらエピタキシャル成
長を行いｎ型層／〕を形成する。この場合、コレクタ領
域に低抵抗の導通路を形成するためヒ素等のｎ型不純物
火高濃度に含む１１ ”層（埋込層）をエピタキシャル
成長の前に形成−することが通常行われる。次に、エピ
タキシャル成長ｎ型層・′ノの上面に酸化膜を成長させ
、これを写真食刻した後、ｐ型不純物例えばホウ素を高
濃度に拡散させｐ 分離領域／３と（〜ｎｎ型層ノー島
状に分離する。次に酸化膜形成、フォトエツチング、拡
散をくり返し７て所要のｐ型領域／４’および、／７、
ｎ 領域１５および／６を得、コンデンサ一部には更に
ＯＶ Ｄ法等により、２酸化シリコン膜７ｇ似形成する
。最後に電極とな、る部分の開［１を１ｊつだ後、表面
全体にアルミニウムを真空蒸危し、配線部を残すように
エツチングを行って配線を形成する。An integrated circuit device having such a structure (which can be made, for example, as follows) using a known method, prepares a p-type silicon substrate and injects an n-type impurity onto its surface. An n-type layer is formed by epitaxial growth while P-bubbling phosphorus into a reaction gas.In this case, a high concentration of n-type impurities such as arsenic is included in order to form a low-resistance conductive path in the collector region. 11" layer (buried layer) is usually formed before epitaxial growth. Next, an oxide film is grown on the top surface of the epitaxially grown n-type layer, and after photoetching this, a p-type layer is formed. A type impurity, such as boron, is diffused at a high concentration to separate the p-type isolation region/3 and (~nn-type layer) into islands.Next, oxide film formation, photoetching, and diffusion are repeated7 to form the required p-type region/4'. and /7,
N regions 15 and /6 are obtained, and a silicon dioxide film 7g is formed on a portion of the capacitor by OVD method or the like. Finally, after opening the part that will become the electrode, aluminum is vacuum evaporated over the entire surface and etched to form wiring so as to leave the wiring part.
このような構ｎ丁の半導体装置中のｎ ｐ ＩＩ ）ラ
ンジスタをコレクタ接地のエミッタフォロアとＬ２て使
用すれば、酸化膜コンデンサのｐ領域／７の電位はｎ領
域ｌ′、２よりも低くなり、こ才１らのｐ ｎ接合は逆
ノζイアスとなるから、酸化膜コンデン゛すにおいて対
基板間に生じていた寄生容量はｐｎ接合による容ｔｏ６
’となり、これが第５図に示すようにエミッタフォロワ
となっているトランジスタのエミッターコレクタ間に存
在し、イぎ号を矢印のようにエミッタからコレクタに戻
すため、直接基板に信号電流が漏洩せず、クロストーク
が悪化しない。If an n p II ) transistor in a semiconductor device with such a structure is used as an emitter follower with a common collector and L2, the potential of the p region/7 of the oxide film capacitor will be lower than that of the n regions l' and 2. , Kosai 1, et al.'s p-n junction has an inverse ζ bias, so the parasitic capacitance that was generated between the substrate and the oxide film capacitor is the capacitance to6 due to the p-n junction.
', and as shown in Figure 5, this exists between the emitter and collector of the transistor that is the emitter follower, and the signal current is returned from the emitter to the collector as shown by the arrow, so that the signal current does not leak directly to the board. , crosstalk is not worsened.
実際の製品では本発明の適用により、数ＤＢないし／θ
数ＤＢのクロストークの改善が見られた。In actual products, by applying the present invention, several DB or /θ
An improvement in crosstalk of several DB was observed.
第６図および第７図は本発明の仙の実施例を示すもので
、第を図の平面図におけるＢ −Ｂ′に沿った断面図が
第７図であり、第３図および第９図と同じ部分には同じ
番号を付している。異なるのは酸化膜コンデンサの導筒
、領域となっているｐ領域７７′の中にｎ＋領領域が形
成されていて、このｎ＋領領域電極２乙によって引き出
されｐ領域７７′から引き出された電極ユＯに共通接続
されている点である。6 and 7 show embodiments of the present invention. FIG. 7 is a sectional view taken along line B-B' in the plan view of FIG. The same parts are given the same numbers. The difference is that an n+ region is formed in the p region 77' which is the conductor and region of the oxide film capacitor, and an electrode drawn out from the p region 77' by this n+ region electrode 2B. This point is commonly connected to UO.
このような構成においてはｎ領域／ノ、ｐ領域／グ、ｎ
＋領領域上ｎｐｎトランジスタとなり、エミッタ領域を
拡大する事により、エミッタ領域上の絶縁膜は、ベース
領域上の絶縁膜に比べて薄くなる為、少ない面積で所定
の容量を得ることができるという利点がある。In such a configuration, n area/no, p area/g, n
By enlarging the emitter region, the insulating film on the emitter region becomes thinner than the insulating film on the base region, making it possible to obtain the desired capacitance with a small area. There is.
第ｇ図は本発明を実際の集積回路に適用した例の一部を
示す回路図であって、ｎｐｎ）ランジスタＱ、＋ 、
Ｑｔをエミッタフォロアとして用い、インピーダンス変
換をした上カップリングコンデンサＣＩ＋０２を介して
入力が行われるλつの差動増幅器を有するビデオ用の集
積回路を示している。FIG.
This figure shows an integrated circuit for video having λ differential amplifiers using Qt as an emitter follower and inputting through an impedance-converted coupling capacitor CI+02.
この回路におけるＱ、とＣ１およびＱ、とＣ７はそれぞ
れ本発明を適用して同一のｎ型領域（島）に形成されて
いる。したがってＱｔ のコレクターエミッタ間および
Ｃ２のコレクターエミッタ間にはそれぞれ酸化膜コンデ
ンサを形成したときのｐｎ接合コンデンサＣ８，および
ＣＦ３２が加わるものの信号電流の漏洩を招く対基板間
の寄生容量はなくなる。In this circuit, Q, C1, and Q, C7 are each formed in the same n-type region (island) by applying the present invention. Therefore, although pn junction capacitors C8 and CF32 are added when forming oxide film capacitors between the collector emitter of Qt and between the collector emitter of C2, there is no parasitic capacitance between the substrate and the substrate that would cause signal current leakage.
以上のように本発明によれば、同一り型領域内にコレク
タ接地されるｎｐｎ トランジスタとｎ型領域を導電領
域とする酸化膜コンデンサとを形成し、この酸化膜コン
デンサのｐ型頭域Ｑｎｐｎトランジスタのエミッタ領域
に電気的に接続しているので、通常酸化膜コンデンサの
導電領域と基板間で生ずる寄生容量がなくなり、エミッ
タフォロアのコレクタ側に信号が戻されるブζめ、クロ
ストークの発生を防止することができる。As described above, according to the present invention, an npn transistor whose collector is grounded and an oxide film capacitor whose collector is grounded in the same type region are formed, and a p-type head Qnpn transistor of this oxide film capacitor is formed. Since it is electrically connected to the emitter region of the oxide film capacitor, the parasitic capacitance that normally occurs between the conductive region of the oxide film capacitor and the substrate is eliminated, and the signal is returned to the collector side of the emitter follower, thereby preventing the occurrence of crosstalk. can do.
第１図は従来の酸化膜コンデンサの構造ケ示す断面図、
第１図は従来の酸化膜コンデンサにおいて生ずる寄生容
ＭＬによりクロストークを生ずる現象を説明する回路図
、第３図は本発明にかかる半導体装１にの一実施例の構
成を示す平面図、第９図は第３図におげろＡＡ’線に沿
った断面を示す断面図、第５図は本発明にかかる半導体
装置における漏洩電流の流れを示す回路図、第を図およ
び第７図は本発明にかかる半導体装置の他の実施例の構
成を示７′畢１４図およびＢＢ’断面図、２； ｇ ｍ
は本発明を実際の集積回路に応用した様子を説明する回
路図である。
１ｌ−ｐ型基板、／−・・ｎ型領域、／３・・・ｐ 領
域、／４’ 、 ／’７ 、 ／７’・−・ｎ型領域、
／６．／乙、パ・・ｎ 領域１、！／ 、 、２２ 、
２３ 、ム・・電極、７ｇ・酸化膜、／夕・・・金属層
１．２亭・・・金属配線。Figure 1 is a cross-sectional view showing the structure of a conventional oxide film capacitor.
FIG. 1 is a circuit diagram explaining the phenomenon of crosstalk caused by parasitic capacitance ML occurring in a conventional oxide film capacitor, FIG. 3 is a plan view showing the configuration of an embodiment of a semiconductor device 1 according to the present invention, and FIG. 9 is a cross-sectional view taken along line AA' in FIG. 3, FIG. 5 is a circuit diagram showing the flow of leakage current in the semiconductor device according to the present invention, and FIG. Figure 7' and BB' sectional view showing the structure of another embodiment of the semiconductor device according to the invention, 2; g m
FIG. 2 is a circuit diagram illustrating the application of the present invention to an actual integrated circuit. 1l-p type substrate, /-... n-type region, /3... p-type region, /4', /'7, /7'... n-type region,
/6. /Otsu, Pa...n Area 1,! / , ,22,
23, M... electrode, 7g, oxide film, / D... metal layer 1.2 Tei... metal wiring.
Claims (1)
接地されるｎｐｎトランジスタと、前記ｎ型領域内にさ
らに形成されたｐ型頭域、その上に形成された酸化膜お
よびさらにその上に形成された金属層により構成される
酸化膜コンデンサとから成り、 前記酸化膜コンデンサの前記ｐ型頭域を前記ｎｐｎトラ
ンジスタのエミッタ領域に電気的に接続した半導体集積
回路要素、 を有する半導体装置。[Claims] An npn transistor formed in an n-type region surrounded by an isolation region and having its collector grounded, a p-type head region further formed in the n-type region, and an oxide film formed thereon. and an oxide film capacitor formed of a metal layer formed thereon, the semiconductor integrated circuit element having the p-type head region of the oxide film capacitor electrically connected to the emitter region of the npn transistor. A semiconductor device with
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58033439A JPS59159560A (en) | 1983-03-01 | 1983-03-01 | Semiconductor device |
| US06/584,506 US4633291A (en) | 1983-03-01 | 1984-02-28 | High-gain semiconductor device with capacitive coupling |
| EP84102129A EP0117566B1 (en) | 1983-03-01 | 1984-02-29 | Semiconductor device having a coupling capacitor |
| DE8484102129T DE3475144D1 (en) | 1983-03-01 | 1984-02-29 | Semiconductor device having a coupling capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58033439A JPS59159560A (en) | 1983-03-01 | 1983-03-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59159560A true JPS59159560A (en) | 1984-09-10 |
Family
ID=12386563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58033439A Pending JPS59159560A (en) | 1983-03-01 | 1983-03-01 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4633291A (en) |
| EP (1) | EP0117566B1 (en) |
| JP (1) | JPS59159560A (en) |
| DE (1) | DE3475144D1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4949150A (en) * | 1986-04-17 | 1990-08-14 | Exar Corporation | Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers |
| JP3039930B2 (en) * | 1988-06-24 | 2000-05-08 | 株式会社日立製作所 | MIS capacitance connection method |
| US4898839A (en) * | 1988-11-15 | 1990-02-06 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit and manufacturing method therefor |
| US5072133A (en) * | 1989-02-16 | 1991-12-10 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets |
| JP2507632B2 (en) * | 1989-10-18 | 1996-06-12 | 株式会社日立製作所 | Semiconductor device |
| JPH10270567A (en) * | 1997-03-21 | 1998-10-09 | Oki Electric Ind Co Ltd | Transistor protective element |
| US6362972B1 (en) | 2000-04-13 | 2002-03-26 | Molex Incorporated | Contactless interconnection system |
| US6612852B1 (en) | 2000-04-13 | 2003-09-02 | Molex Incorporated | Contactless interconnection system |
| US7466212B2 (en) * | 2006-06-16 | 2008-12-16 | Semiconductor Components Industries, L. L. C. | Semiconductor filter structure and method of manufacture |
| US7589392B2 (en) * | 2006-06-16 | 2009-09-15 | Semiconductor Components Industries, L.L.C. | Filter having integrated floating capacitor and transient voltage suppression structure and method of manufacture |
| US7579670B2 (en) * | 2006-07-03 | 2009-08-25 | Semiconductor Components Industries, L.L.C. | Integrated filter having ground plane structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1241285A (en) * | 1970-02-02 | 1971-08-04 | Mullard Ltd | Improvements relating to neutralised transistor amplifiers |
| US4214252A (en) * | 1977-08-06 | 1980-07-22 | U.S. Philips Corporation | Semiconductor device having a MOS-capacitor |
| US4211941A (en) * | 1978-08-03 | 1980-07-08 | Rca Corporation | Integrated circuitry including low-leakage capacitance |
| US4245231A (en) * | 1978-12-26 | 1981-01-13 | Motorola Inc. | Combination capacitor and transistor structure for use in monolithic circuits |
| JPS5685848A (en) * | 1979-12-15 | 1981-07-13 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| US4386327A (en) * | 1979-12-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Integrated circuit Clapp oscillator using transistor capacitances |
| JPS57206062A (en) * | 1981-06-12 | 1982-12-17 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1983
- 1983-03-01 JP JP58033439A patent/JPS59159560A/en active Pending
-
1984
- 1984-02-28 US US06/584,506 patent/US4633291A/en not_active Expired - Lifetime
- 1984-02-29 DE DE8484102129T patent/DE3475144D1/en not_active Expired
- 1984-02-29 EP EP84102129A patent/EP0117566B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3475144D1 (en) | 1988-12-15 |
| EP0117566A2 (en) | 1984-09-05 |
| EP0117566B1 (en) | 1988-11-09 |
| US4633291A (en) | 1986-12-30 |
| EP0117566A3 (en) | 1986-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3702428A (en) | Monolithic ic with complementary transistors and plural buried layers | |
| JPS59159560A (en) | Semiconductor device | |
| JPS6229904B2 (en) | ||
| US5027183A (en) | Isolated semiconductor macro circuit | |
| US4160989A (en) | Integrated circuit having complementary bipolar transistors | |
| JPS6323335A (en) | Isolation and substrate connection for bipolar integrated circuit | |
| JPH01123440A (en) | Semiconductor device | |
| JPH06112217A (en) | Semiconductor device and its manufacture | |
| JP2587424B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP2723724B2 (en) | Semiconductor device | |
| JPS6173364A (en) | Semiconductor integrated circuit device | |
| JPS5874066A (en) | Semiconductor ic device | |
| JPS59145569A (en) | Multicollector vertical p-n-p transistor | |
| JPS59181058A (en) | Semiconductor device | |
| JP3173184B2 (en) | Semiconductor device | |
| JPS5812343A (en) | Semiconductor device | |
| JPS6153756A (en) | Semiconductor device | |
| JPS61127157A (en) | Semiconductor device | |
| JP2783888B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2633374B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS60249363A (en) | Semiconductor ic device | |
| JPH05343411A (en) | Semiconductor device and manufacture thereof | |
| JPS6224659A (en) | Complex junction capacitor | |
| JPH04309232A (en) | Bipolar transistor and its manufacture | |
| JPS60119770A (en) | Semiconductor device |