JPS5915875A - Compensation of strain of interface circuit in automatic test device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic circuits and, more particularly, to a method for mutually correcting distortion of a group of interface circuits in an automatic test system.

In automatic test equipment for testing integrated circuits,
A plurality of bin electronics interface circuits are connected to the bins or nodes of the electronic device under test. Through these bins, excitation signals are provided to the device under test, and output signals from the device under test are sensed and measurements are made. Typically, such excitation signals represent logic states, analog voltages or currents to be applied in a parallel pattern to the bins of the device under test, and the output signals resulting from the test are examined in parallel.

These interface circuits serve as an interface between the computer controlling the test system and the individual bins of devices under test. These interface circuits receive reference voltages and digital data from other circuits in the test system and, via drivers, transfer these voltages or data to the output under test under the control of a program stored in the test system computer. Switch the device to the desired bin. Correspondingly, the interface circuit receives a reference voltage or data from the device under test and sends it to a comparison circuit for comparing the received signal with the appropriate response stored within the program of the test system computer. supply In this way, individual electronic components, such as semiconductor memories, microprocessors, etc., are individually tested to meet the desired standards and specifications required by terminal users of such devices. ensure that

One of the problems that arises in operating such automated test equipment is the propagation of signals to and from the device under test through such interface and connection circuits. Differences in time delays create time distortions in both the excitation signal and the monitored response.

Such time distortions make it more difficult to apply the desired excitation signal in a simultaneous parallel pattern to the input bins of the device under test, and even if the device under test is providing accurate output signals. This makes it difficult to decide whether or not.

One conventional technique for determining the time distortion of both the excitation signal and the monitored condition is to connect each pin electronics interface circuit to a standard or reference interface circuit and calculate the relative distortion between these circuits. It's about measuring.

Such a configuration is used in the Takeda RIKEN automatic test system that uses a coaxial relay multiplexer.

In principle, this system uses 1:4 relay multiplexers, and four interface circuits are connected to each multiplexer. The output signals from four such multiplexers are fed as inputs to another 1=4 multiplexer. In the end, 1
Only 1=4 multiplexers are needed, which are connected to the reference interface circuit. In this way, by controlling the banks of multiplexers accordingly, it is possible to connect any interface circuit to the reference circuit and to determine the distortion of that circuit. However, this technique has several drawbacks.

First, this technique requires a large number of relatively expensive coaxial multiplexers. The use of such a large number of multiplexers reduces reliability and increases the physical size of the test equipment.

By using higher multilevels, e.g. 1:8
Although it is possible to reduce the number of multiplexers by doing so, this increases the capacitive load of the system and slows down its operating speed.

The present invention has been made in view of the above points, and an object of the present invention is to eliminate the drawbacks of the prior art as described above.

The present invention provides a method for measuring the distortion characteristics of each interface circuit relative to other interface circuits and then correcting the sensed distortion. The present invention does not require any additional equipment over what is conventionally provided in a test system, and eliminates the need to provide one large coaxial multiplexer and several reference interface circuits. Excluding. The present invention provides two
A method for mutually correcting distortion of m interface circuits, the method comprising: (1) a path between a first driver and a first comparator; and (2) a path between the first driver and a second comparator.

(3) The propagation delay in each path between the second driver and the first comparator and (4) the path between the second driver and the second comparator is measured, and based on the following equation: Calculate the relative driver distortion and relative comparator distortion, (3-2) 10, (4-1) relative driver distortion − (4-1) −(3-2> relative comparator distortion =−−1) Then, ii! the delay means for each of the driver and comparator to correct the calculated distortion!
! It is characterized by the fact that it is divided into sections.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figure 1 shows the marker generator 1
FIG. 5 is a simplified block diagram illustrating 5 and a pair of interface circuits associated therewith. Each interface circuit includes a driver 18 and a comparator 20
and other components. Marker generator 15 provides a timing signal via wiring 17;
Wiring 17 fans out to two drivers 18a and 18b. The output of the fan-out device 22 has some distortion, that is, the output signal supplied to the driver 1 via the wiring 23a does not necessarily match the timing of the output signal supplied to the driver 2 via the wiring 23b. do not have. At the output side of the driver there are delays dl and dl. In many automated test systems,
These delays are programmable or adjustable using known equipment. Although there may be a difference in delay before and after the driver, for the purpose of the present invention it is not important what causes the delay, so in Figure 1 has this kind of delay in driver 1
Only the output side of 8 is shown. The delay elements d and dl are adjustable to adjust the time delay of the signals propagated from the marker generator 15-fJl so that these signals reach the nodes n1 and n.
It is possible to adjust to reach 2 at the same time.

The delay dC existing between nodes n1 and n2 represents the delay that inherently exists when a signal is transmitted from one node to the other. Nodes n+ and n2
and each comparator 20 has an additional delay CI
and C2 are present.

When calibrating the system illustrated in FIG. 1, the desired signal, for example the rising edge or the falling edge of a pulse, is provided by the marker generator 15.

Four timing measurements are then taken. These four timing measurements are: (1) the time delay inherent in the transmission from driver 1 to comparator 1; and (2) the transmission from driver 1 to comparator 2 via delay element dC. the time delay inherent in the case,
This means measuring the time delay between (3) the driver 2 and the comparator 1 via the delay element dC, and (4) the time delay between the driver 2 and the comparators 2 and 8-.

The following calculations are performed using these measured time delays. Note that tl and tz are each driver and delay element d1
or dl.

ηu = i+ + d+ 10+ η12 = dc + tl + d+ +02ηη−
t2+62 + 02 η21= dc + tz +d2+(1+η21−η
+2=(t2+d2)-(tl+d+)+cI-0
2ηη−η++ = (jz + dl) −(j+
+ d+ ) + 02- C+, that is, (η21-η12) + (η22-ηn) Driver distortion -□□- = (tz+d2)-(t++d+)(ηη-ηu
) −(η21−η12) Comparator distortion = □□ = (02−C+) Therefore, the last two equations in the above equations are equations that define the relative driver distortion and the relative comparator distortion. Since it is possible to adjust the delay elements on the test head itself, the timing of the drivers and comparators can be made accurate relative to each other by adjusting the delay elements associated with, or connected to, each driver and comparator. It is possible to calibrate to

FIG. 2 is a block diagram illustrating that it is possible to perform distortion correction even in the case of three or more circuits by expanding the technique described in connection with FIG. 1. As shown in FIG. 2, marker power is applied individually to each of the four interface circuits and the resulting time delay is determined.

Although the configuration shown in Figure 2 uses a bidirectional coaxial ring bus, the particular ring configuration is not important in this case (other configurations may be used as well). For example, it is possible to use star arrays, star clusters, etc. In the same way as described with respect to FIG. However, the function of this system as a whole is to measure distortion in a combination circuit of four or more interface circuits and perform distortion correction.

FIG. 3 shows in detail the case in which four interface circuits are interconnected to form the ring bus structure shown in FIG. 2. The configuration shown in FIG. 3 includes interface circuits 30, 31, 32.33. As shown, each reference driver is connected to a marker generator 37 via a logic gate 35. The system driver is also connected to the marker generator, although these do not necessarily have to be the same. Each interface circuit has a group of elements. For example, the interface circuit 31 includes a system driver 41b, a reference driver 42b, and a multiplexer 43b. The comparator side of the device under test (DLJT) includes a multiplexer 44b, a system comparator 45b at 11-, and a reference comparator 4.
6b and a multiplexer 47b. In operation, as shown, the device under test is connected between multiplexers 43b and 44b. The switches shown between multiplexers 43 and 44 for each of the interface circuits allow the reference driver, system driver, reference comparator or system comparator to be connected to the device under test as appropriate.

The drivers and comparators of the interface circuit shown in FIG. 3 are interconnected to determine their relative distortions in the same manner as described with respect to FIGS. 1 and 2. The relative driver timing distortion and the relative comparator timing distortion are then measured using the same techniques described with respect to FIG. to correct.

Driver distortion can be determined and corrected independently of comparator distortion, and vice versa.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course it is.

[Brief explanation of the drawing]

Figure 1 is a schematic block diagram illustrating a state in which the distortion of an interface circuit is measured with respect to the distortion of other interface circuits, and Figure 2 is a schematic diagram illustrating a state in which distortions of four interface circuits are measured with respect to each other. FIG. 3 is a detailed block diagram of the apparatus shown in FIG. 2. (Explanation of symbols) 15: Marker generator 18: Driver 20: Comparator 22: Fan-out devices c, d: Delay element n: Node patent applicant Fairchilde Camera and Instrument Cohoction Procedure Amendment 1982 July 19, 2006 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1, Indication of the case 1981 Patent Application No. 9
0111 No. 3, Relationship with the amended party case Patent applicant Corporation 4, agent 5. Date of amendment order Voluntary 8, Contents of amendment As attached.

Claims (1)

Claims: 1. A method for distortion correcting a first interface circuit with respect to a second interface circuit, each interface circuit having a driver, a comparator, and an adjustable delay means, comprising: (1) (2) a path from the first driver to the second comparator; (3) a path from the second driver to the first comparator; and (4) a path from the second driver to the first comparator. measuring a propagation delay in each of the paths to a second comparator, calculating a relative driver propagation delay and a relative comparator propagation delay, and determining the adjustable delay to compensate for the calculated propagation delay; A method characterized by adjusting the means. 2. The method according to item 1 above, wherein in the step of making the adjustment, the propagation delay of the adjustable delay means is changed. 3. The method according to item 2 above, characterized in that, in the step of performing the measurement, a marker signal is supplied to each of the first driver and the second driver. 4. In the above item 3, in the step of performing the measurement, a propagation delay necessary for the marker signal to reach each of the first driver and the second driver is further determined. How to do it. 5. The method of item 4 above, wherein each of the first interface circuit and the second interface circuit includes both a reference comparator and a reference driver.