JPS59155959A - Power transistor - Google Patents
Power transistorInfo
- Publication number
- JPS59155959A JPS59155959A JP3034683A JP3034683A JPS59155959A JP S59155959 A JPS59155959 A JP S59155959A JP 3034683 A JP3034683 A JP 3034683A JP 3034683 A JP3034683 A JP 3034683A JP S59155959 A JPS59155959 A JP S59155959A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- layers
- power transistor
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 208000034888 Needle issue Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000001467 acupuncture Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は使用時における破壊１針量を上昇させること
ができる゛電力用トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a power transistor capable of increasing the amount of one needle broken during use.
〔発明の技術的背景及びその問題点Ｊ
′酸方力用トランジスタおける欠陥の一つに熱正帰還に
よる′電流集中破壊現象がある。このような現象により
で陽性の使用条件が制限され、たシ、装置の設計に余分
なマージンが必要になるという問題があった。このため
、トランジスタの破壊耐敬を上げる方法が種々提案され
ている。例えば、トランジスタのエミッタ領域にバラン
ス抵抗を介在させるもので、第１図を用いてその一例に
ついて説明する。[Technical Background of the Invention and Problems Therewith J'One of the defects in acid transistors is the 'current concentration breakdown phenomenon' caused by thermal positive feedback. This phenomenon limits the conditions for positive use and requires extra margin in the design of the device. For this reason, various methods have been proposed to increase the breakdown resistance of transistors. For example, a balance resistor is interposed in the emitter region of a transistor, and an example thereof will be explained with reference to FIG.
第１図（Ｎはエミッタ領域にバランス抵抗が介挿された
電力用トランジスタの平面図、第１図ω）は第１図（４
）に示した平面図のＡ−Ａ′線に沿った断面図である。Figure 1 (N is a plan view of a power transistor in which a balance resistor is inserted in the emitter region, Figure 1 ω) is
) is a sectional view taken along line AA' of the plan view shown in FIG.
第１図において、１はＮｕコレクタ層、２はＰ型ベース
晴、３は上記ベース層２に分離形成された複数のエミツ
タ層、４は絶縁膜、５は上記絶縁膜４上で上記エミツタ
層３とそれぞれ接触した例えばポリシリコンで形成され
たバランス抵抗、６は上記絶縁膜４上で各バランス抵抗
５を共通接続する三ミッタ電極、７は上記エミツタ層３
に接触された分離エミッタ電極、８はペース電極、９は
コレクタ電極である。第１図に示した電力用トランジス
タは分離形成された多数のエミツタ層３がパラシス抵抗
５を介して共通接続されているため、エミッタ電流が均
等に分配されて電流集中が起こりに〈くなる。この結果
、大きな破壊耐量が得られる。In FIG. 1, 1 is a Nu collector layer, 2 is a P-type base layer, 3 is a plurality of emitter layers formed separately on the base layer 2, 4 is an insulating film, and 5 is the emitter layer on the insulating film 4. 3 is in contact with a balance resistor made of polysilicon, for example; 6 is a three-mitter electrode that commonly connects each balance resistor 5 on the insulating film 4; 7 is an emitter layer 3;
8 is a pace electrode and 9 is a collector electrode. In the power transistor shown in FIG. 1, a large number of separately formed emitter layers 3 are commonly connected through a parasitic resistor 5, so that the emitter current is evenly distributed and current concentration is prevented. As a result, a large amount of destruction resistance can be obtained.
しかし、製造技術的にみれば抵抗ｌ脅５を設けることに
より、絶縁ｊ換４との間に段差ができる。However, from a manufacturing technology point of view, by providing the resistor 5, a step is created between the resistor 5 and the insulator 4.
従って、’ｒＲ極６を形成するために行なわれるアルミ
ニウム蒸着時に配線段切れが生じやすいという欠点があ
る。従って、ポリシリコンで形成されたバランス抵抗５
は上記した理由からあまり厚く出来ない。このた゛め、
多数に分割し電流を９＋１記しても抵抗層の町°敬がそ
の大きさで制限されてしまうという問題があった。Therefore, there is a drawback that wiring breaks are likely to occur during aluminum evaporation to form the 'rR pole 6. Therefore, the balance resistor 5 made of polysilicon
cannot be made very thick for the reasons mentioned above. Because of this,
Even if the current is divided into many parts and the current is written as 9+1, there is a problem in that the resistance of the resistance layer is limited by its size.
さらに ；；ｆＧ １図に示したバランス抵抗５を拡散
により形成するようにした電力用トランジスタも考えら
れている。このようなトランジスタについて説り］する
。第２図において、１１はＮ型コレクタ層、１２はＰ型
ベース層、１３は上記ベース層１２に分離形成された複
数のエミツタ層、１４は絶縁ｊ１ば、１５は複数のエミ
ツタ層Ｉ３に接続されて形成されたＮ型抵抗ｒｙ５，１
ｅは上記抵抗層１５とコンタクト共通接続されたエミッ
タ電極、１７はベース′電極、１Ｂはコレクタ電極であ
る。Furthermore, a power transistor in which the balance resistor 5 shown in FIG. 1 is formed by diffusion is also being considered. I will explain about such a transistor]. In FIG. 2, 11 is an N-type collector layer, 12 is a P-type base layer, 13 is a plurality of emitter layers formed separately on the base layer 12, 14 is an insulation layer, and 15 is connected to a plurality of emitter layers I3. N-type resistor ry5,1 formed by
Reference numeral e designates an emitter electrode commonly connected to the resistance layer 15, 17 a base' electrode, and 1B a collector electrode.
第２図に示したような電力用トランジスタは第１図に示
したような電力用トランジスタと同様な効果が考えられ
る。しかし、第２図に示したような電力用トランジスタ
はトランジスタの動作状態において、抵抗層１５は大電
流で発熱を起こしてしまい、抵抗層１５自身がエミッタ
として注入を始めてしまうという現象が生じる。The power transistor shown in FIG. 2 is considered to have the same effect as the power transistor shown in FIG. 1. However, in the power transistor shown in FIG. 2, when the transistor is in operation, the resistance layer 15 generates heat due to a large current, and a phenomenon occurs in which the resistance layer 15 itself starts to be injected as an emitter.
このため、抵抗としての働きを半減させてしまい期待す
るほどの大きな効果が得られないという欠点があった。For this reason, there was a drawback that the function as a resistor was reduced by half, and the expected effect could not be obtained.
さらに、電力用トランジスタの破壊耐量を上げる他の方
法としてベースにバランス抵抗を入れ、ベース電流を制
御する方法がある。第゛３図はそのようにしてベース電
流を制御している電力用トランジスタを示す断面図であ
る。第３図において、２１はＮ型コレクタ層、２２はｂ
型ベース層、２３はエミツタ層、２４は絶縁膜、２５は
上記ベース層２２に形成され、上記エミッタｊ脅２３と
ベース電極２７との間に位置したＮ型ベース分離層、２
６は上記エミツタ層２３に接触されたエミッタ電極、２
７はベース電極、２８はコレクタ電極である。第３図に
示したようなトランジスタにおいてはＮ型分ＦＢＩ ｉ
＠２５ ｉｉ下のベース層２２がベースｌ−流のバラン
ス抵抗として１動き、エミッタ全域にわたって均一に電
流を分配することができる。Furthermore, another method for increasing the breakdown resistance of a power transistor is to insert a balance resistor into the base and control the base current. FIG. 3 is a sectional view showing a power transistor controlling the base current in this manner. In FIG. 3, 21 is an N-type collector layer, 22 is b
a type base layer; 23 is an emitter layer; 24 is an insulating film; 25 is an N-type base separation layer formed on the base layer 22 and located between the emitter layer 23 and the base electrode 27;
6 is an emitter electrode in contact with the emitter layer 23; 2;
7 is a base electrode, and 28 is a collector electrode. In a transistor like the one shown in Fig. 3, the N-type component FBI i
@25 ii The underlying base layer 22 acts as a balance resistor for the base l-flow and can distribute the current uniformly across the emitter.
しかし、第３図に示した′巨カ用トランジスタにおいて
はベース層２２を直接、抵抗として使用しているもので
あるから、さらにその効果を上げるためにベース層２２
の抵抗を上げると、ベース中の正孔ｆ３度が低くなる。However, in the large power transistor shown in FIG. 3, the base layer 22 is directly used as a resistor, so in order to further increase the effect, the base layer 22
Increasing the resistance of , the hole f3 degree in the base decreases.
このために、早く伝導変調を起こし、電流利得を下げる
という欠点があった。さらに、高電流における電流利得
の低下は鍼刀用トランジスタにおいては１♀−に問題と
なる場合が多い。This has the disadvantage of causing conduction modulation quickly and lowering the current gain. Furthermore, reduction in current gain at high currents often poses a problem in 1♀- transistors for acupuncture.
この発明は上記の点に鑑みてなされたもので、その目的
はバランス抵抗をベース層に分離形成させ、トランジス
タ動作時におけるエミッタ′「電流を均一に５＋６己し
、破壊酌量を上げるようにした′電力用トランジスタを
提供することにある。This invention was made in view of the above points, and its purpose is to separate and form a balance resistor in the base layer, so that the emitter current is uniformly distributed during transistor operation, and the damage allowance is increased. The purpose of the present invention is to provide a power transistor.
バランス抵抗をベース層に分離形成させ、トランジスタ
動作時におけるエミッタ電流を均一に分配し、破壊耐量
を上げるようにしている。A balance resistor is formed separately in the base layer to uniformly distribute emitter current during transistor operation and increase breakdown resistance.
以下、図面を参照してこの発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第４図はこの発明の一実施例に係る′電力用トランジス
タを示すもので、第４図（Ａ）は平面図、第４図（Ｂ）
は第４図（勾に示した平面図のＡ−ｐ！線に沿った断面
図である。第４図において、ｎｐｎ型プレ〜ナトランジ
スタを製造する場合について説明する。まず、Ｎ型半導
体基板３１を水蒸気雰囲気中で高温酸化を行い、５ｉ０
２層３４を形成する。そして、上記５ｉ０４層３４を写
真蝕刻法によりベース領威形成のため選択拡散の孔を開
け、硼素原子を拡散してＰ型ペースＩ＠３２を形成する
。この場合の拡散は酸化性雰囲気で行々われ、硼素原子
が拡散すると同時にベース層３２主面に再び５ｉ０２４
を形成させる。次に、上記ベース層３２にリン原子の選
択拡散によりＮ型エミツタ層３３及びｎ型抵抗層３５を
形成する。上記エミツタ層３３及び抵抗層３５ばＯ１１
６形成され、８１０２層を再び写真［刊１刻法により開
孔した後アルミニウムを真空蒸着する。そして、写真蝕
刻法により、エミッタ電極３６、ペース司： ５３３７
、ベースコンタクト電極３７１を分離形成する。この
、碌にして、分割されたエミツタ層３３及び抵抗層３５
は共辿接続される４）ｋに配ｔばされる。また、コレク
タ電極３８はニッケル金属のメッキ又は真を蒸着等によ
り形成はれる。FIG. 4 shows a power transistor according to an embodiment of the present invention, FIG. 4(A) is a plan view, and FIG. 4(B) is a top view.
is a sectional view taken along the A-p! line of the plan view shown in FIG. 31 was oxidized at high temperature in a steam atmosphere to give 5i0
Two layers 34 are formed. Then, holes for selective diffusion are formed in the 5i04 layer 34 by photolithography to form a base region, and boron atoms are diffused to form a P-type paste I@32. The diffusion in this case is carried out in an oxidizing atmosphere, and at the same time as the boron atoms are diffused, 5i024 is again deposited on the main surface of the base layer 32.
to form. Next, an N-type emitter layer 33 and an n-type resistance layer 35 are formed in the base layer 32 by selective diffusion of phosphorus atoms. The emitter layer 33 and the resistance layer 35 O11
6 was formed, and the 8102 layer was again opened by the photolithography method, and then aluminum was vacuum-deposited. Then, by photolithography, emitter electrode 36, pace electrode 5337
, a base contact electrode 371 is formed separately. This improved and divided emitter layer 33 and resistance layer 35
are distributed to 4) k, which are co-traced connected. Further, the collector electrode 38 is formed by plating nickel metal or by vapor deposition.
以上詳述したようにこの発明によれば、バランス抵抗を
ベース層に５＋離形成させ、トランジスタ仮１作時にお
けるエミッタ電極を均一に分配するようにしたので、破
壊耐滑を上げることができる。さらに、ベース層におけ
る伝導度変調も起こしにくい電力用トランジスタを提供
することができる。As described in detail above, according to the present invention, the balance resistor is formed at a distance of 5+ from the base layer, and the emitter electrodes are evenly distributed during temporary operation of the transistor, so that the breakdown resistance can be improved. Furthermore, it is possible to provide a power transistor in which conductivity modulation in the base layer is less likely to occur.
第１図（１０は従来の電力用トランジスタの平面図、第
１図（Ｂ）は第１図（４）のＡ−Ａ′線に沿った断面図
、第２図及び第３図・はそれぞれ従来の′電力用トラン
ジスタの断面図、第４図囚はこの発明の一実施例に係る
′電力用トランジスタの平面図、第４図（Ｂ）は第４図
（Ａ）に示しだトランジスタの八−へ′断面図である。
３１・・・Ｎ型半導体基板、３２・・・ベースＪ愕、３
３・・・エミツタ層、３４・・・５ｉ０２層、３５・・
・抵抗層。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
第３図
８
第４図Figure 1 (10 is a plan view of a conventional power transistor, Figure 1 (B) is a sectional view taken along line A-A' in Figure 1 (4), Figures 2 and 3 are respectively FIG. 4 is a cross-sectional view of a conventional power transistor, FIG. 4 is a plan view of a power transistor according to an embodiment of the present invention, and FIG. 31... N-type semiconductor substrate, 32... Base J-shaped, 3
3...Emitsuta layer, 34...5i02 layer, 35...
・Resistance layer. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 8 Figure 4
Claims (1)
ース領域内に分離形成された上記エミッタ領域と同伝導
型の複数の拡散抵抗層とを具備し、上記拡散抵抗層を介
してペース１！極を取出すようにしたことを特徴とする
電力用トランジスタ。A plurality of emitter regions and a plurality of diffused resistance layers of the same conductivity type as the emitter regions are formed separately in a pace region opposite to the emitter regions, and the paste 1! A power transistor characterized by having a pole removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034683A JPS59155959A (en) | 1983-02-25 | 1983-02-25 | Power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034683A JPS59155959A (en) | 1983-02-25 | 1983-02-25 | Power transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59155959A true JPS59155959A (en) | 1984-09-05 |
| JPH0475658B2 JPH0475658B2 (en) | 1992-12-01 |
Family
ID=12301274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3034683A Granted JPS59155959A (en) | 1983-02-25 | 1983-02-25 | Power transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155959A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275175A (en) * | 1987-05-07 | 1988-11-11 | Fuji Electric Co Ltd | Power transistor |
| US5387813A (en) * | 1992-09-25 | 1995-02-07 | National Semiconductor Corporation | Transistors with emitters having at least three sides |
-
1983
- 1983-02-25 JP JP3034683A patent/JPS59155959A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275175A (en) * | 1987-05-07 | 1988-11-11 | Fuji Electric Co Ltd | Power transistor |
| JPH0577332B2 (en) * | 1987-05-07 | 1993-10-26 | Fuji Electric Co Ltd | |
| US5387813A (en) * | 1992-09-25 | 1995-02-07 | National Semiconductor Corporation | Transistors with emitters having at least three sides |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0475658B2 (en) | 1992-12-01 |
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