JPS59154883A - Video signal discriminating circuit - Google Patents

Abstract

PURPOSE:To attain normal logical processing between a synchronizing signal and the output of an oscillator with fidelity by forming a signal with a delay time from the output signal of a synchronizing signal generating circuit and inputting said signal to an AFC circuit. CONSTITUTION:A composite video signal (a) inputted from a terminal 1 is inputted to the synchronizing signal generating circuit 2 to form a synchronizing signal (b). This synchronizing signal (b) is applied to an NAND circuit 5 and a delay circuit, from which a pulse signal (c) having a prescribed time delay is outputted and inputted to the AFC circuit 3, the phase is compared with the output of the oscillator 4, and a detecting signal (d) synchronizes an output (f) of the oscillator with a delay synchronizing signal (c). The output (f) is NAND- processed with the synchronizing signal (b) at an NAND circuit 5 and an output (h) is obtained.

Description

[Detailed description of the invention] The present invention relates to a video signal discrimination circuit.

Generally, in color televisions and VTRs, when the regular TV double signal is not input during channel tuning or switching, unpleasant noise may occur. The ink circuit is wide (S), and an automatic frequency fine-run circuit (Automatic Fine-run) is temporarily installed to accurately match the frequency during channel tuning.
ing; AFT) is widely used. In such a device, a video signal discrimination circuit is required to determine whether the composite video signal is a regular signal or not, and to generate a mute signal or an AFT operation stop signal if the composite video signal is not a regular video signal.

Conventionally, there has been a device of this type as shown in FIG.

In the figure, (1) is a composite video signal input terminal, (2) is a synchronization signal generation circuit that separates and outputs a synchronization signal from the composite video signal a, and (14) is a free-running oscillation at a frequency near the horizontal synchronization signal frequency. (3) is an automatic frequency control circuit (hereinafter referred to as AFC circuit) for adjusting the phase of the output signals e and f of the oscillator 14) to the synchronization signal (hereinafter referred to as AFC circuit), +5
Reference numeral 1 designates an output NAND circuit which outputs the synchronizing signal generating circuit (2). Note that (6) is the output terminal of the NAND circuit (5).

Next, the operation will be explained.

When the composite video signal λ input from the input terminal (1) is input to the synchronization signal generation circuit (2), it is synchronously separated and the synchronization signal is output. One of the synchronization signals is AF
C circuit (3), where the output e of the oscillator (4)
and an output d corresponding to the phase difference is input to the oscillator 14), whereby the phase of the output e of the oscillator 14) is matched with the phase of the synchronizing signal S. Next, oscillator 1
The output f that has the same phase as the output e of 4) is a NAND circuit (5)
Another synchronizing signal is input to this NAND circuit (5), and this NAND circuit (5)
5) outputs i(high) if one of the two inputs is Low, and both inputs output t(
Outputs Low only when it is high. In other words, N
What is the output of the AND circuit (5)?

If the frequency of the synchronizing signal deviates beyond the pull-in range of the AFC circuit (3), the operation of the audio output ring and AFT will be suppressed.

＼ (3) For example, now, composite video signal 3 with little noise is connected to terminal (1
) is input to the synchronization signal generation circuit (2) and the synchronization-separated synchronization signal is as shown in FIG. Figure (b
). The synchronizing signal and the output f of the oscillator (4) are input to the NAND circuit (5), and the NAND-processed output is as shown in FIG. 2(C). Since the input signal 3 at this time has little noise, it is shown in Fig. 2 (a).
) (b) As can be seen from (C), the AFC circuit (3)
When the oscillator 14) operates correctly and the synchronizing signal is normally output, NANI) processing is performed with the output f of the oscillator 14), and a normal video signal discrimination signal is obtained.

Next, when a noisy composite video signal l is input from the terminal (1) to the synchronization signal generation circuit (2), this circuit (2)
The output b1 of is also a noisy synchronization signal. In this case 4
Because the synchronization signal b1 contains a lot of noise,
Apc circuit (3) is affected by noise.

For example, if the synchronization signal b1 at this time is shown in Figure 2(d), the AFC circuit (3) will match the phase with the noise, and the output f1 of the two oscillators (4) will be as shown in Figure 2(e).
14) The falling edge of this output f1 is the synchronization signal b1.
It will be faster than . Therefore, the output h1 obtained by NANDing the output [1 and the synchronization signal of the oscillator 14) is shown in Fig. 2(f).
As shown in the figure, the NAND processing with the synchronization signal is not performed normally (therefore, if a noisy signal is input, the output h1 of this NAND circuit (5) is used to perform the AF
When stopping the T circuit or stopping the audio, it may cause malfunction. For example, even if a TV signal is input, the AF
The operation of the T will be stopped or the sound will be muted.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by creating a signal delayed by a certain time from the output signal of the synchronization signal generation circuit and inputting this signal to the AFC circuit, the synchronization signal can be generated. A video signal discriminator circuit that can faithfully and correctly perform logical processing between the output of the oscillator and the output of the oscillator even when a noisy signal is input, and that can reliably and accurately stop the AFT circuit and stop the audio. is intended to provide.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a video signal discrimination circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts. (7) is a delay circuit which delays the output signal of the synchronizing signal generating circuit (2) by a certain period of time and outputs a pulse signal C. Furthermore, in this embodiment, a delayed synchronization signal C is input to the AFC circuit (3) instead of the synchronization signal S.

Next, the operation will be explained.

Now, the composite video signal a input from the terminal (1) is input to the synchronization signal generation circuit (2), which separates the synchronization and outputs the synchronization signal. One of these synchronizing signals is input to the NAND circuit (5), and the output f of the oscillator 14)
and NAND processing is performed. Another synchronizing signal C is input to a delay circuit (7), and a pulse signal C which is activated at a certain time is outputted in response to this synchronizing signal S. This delayed synchronization signal C is input to the AFC circuit (3), and its phase is compared with the output e of the oscillator 14).
The circuit (3) synchronizes the outputs e, f of the oscillator 14) with the delayed synchronization signal C. Of the outputs e and f of this oscillator (4), the output f is input to the NAND circuit (5), and the synchronizing signal is NANDed, and the output of the NANO circuit (5) is output to the output terminal (6). be done.

For example, the composite video signal with low noise is connected to the terminal (1).
, the output signal of the synchronization signal generation circuit (2) becomes as shown in Fig. 4(C), and the delayed synchronization signal C, which is obtained by delaying this signal by a certain period of time, is as shown in Fig. 4(a). It becomes as shown in . The output f of the oscillator 14) is shown in FIG. 4(b).
). The output obtained by NANDing the output f of the oscillator (4) and the output of the synchronizing signal generating circuit (2) is as shown in FIG. 4(d).

Next, when the noisy composite video signal 11 is input to the terminal (1), the output b1 of the synchronization signal generation circuit (2)
The waveform becomes as shown in figure (g), and one side of this signal b' enters the +x N A N 0 circuit (5), and the oscillator (4)
It is NANDed with the output f1 of. Synchronous signal generation circuit (
The other output b' of 2) is input to the delay circuit (7), and the signal C' delayed by a certain period of time becomes as shown in FIG. 4(e). This seven signal c+ is input to the AFC circuit (3), and the oscillator (4) is controlled so that the phase of the output f1 matches the phase of the delayed synchronization signal C1, and is output. Therefore, the output 1' of this oscillator +41 becomes as shown in FIG. 4(f).

Next, the output f1 of the oscillator (4) is output from the synchronization signal generation circuit (2).
) is NANDed with the output bl and output h to the terminal (6).
' [see FIG. 4(h)] is output. If there is a lot of noise, the AFC circuit (3) will be activated by the noise of the output signal b' of the synchronization signal generation circuit (2) as shown in Fig. 4(f), and synchronization will occur slightly before the rear edge of the delayed synchronization signal C1. However, even in such a case, the synchronizing signal and the output f' of the oscillator 14)
The NAND processing with will be performed accurately.

Therefore, the AFT circuit and the audio can be stopped without the NAND circuit being affected by noise.

As described above, according to the present invention, the synchronization signal is delayed and the A
Since it is input to the FC circuit, the NANI) processing of the synchronization signal and the output of the oscillator can be performed faithfully even when the signal is noisy, which has the effect of suppressing malfunctions when the signal is noisy. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional video signal discrimination circuit, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG. 3 is a block diagram showing a video signal discrimination circuit according to an embodiment of the present invention. FIG. 4 is a signal waveform diagram of each part in FIG. 3. Note that the same reference numerals in the figures indicate the same or similar parts. Agent Makoto Kuzuno - Figure 1 (f) h'-1-1] [Procedural amendment (voluntary) 21 Title of invention Video signal discriminator circuit 3, relationship with the person making the amendment Patent applicant address Tokyo 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Co., Ltd. Representative: Katayuni 8be 4, Agent address: 5, Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Detailed description of the invention in the subject specification and drawings (Figures 2 and 4)
Correct to "during detuning operation". (2) On page 3, line 20, "suppress" is corrected to "stop." (3) Correct "delayed signal" on page 7, line 19 to "delayed signal." (4) In the first line of page 8, "(4) is" is corrected to "(4) is". (5) Figures 2 and 4 are corrected as shown in the attached sheet. Above Figure 2 Figure 4

Claims (1)

[Claims] (1) A synchronization signal generation circuit that extracts a synchronization signal from a composite video signal, a delay circuit that delays the output of the synchronization signal generation circuit for a certain period of time, an oscillator that free-runs at a frequency near the horizontal synchronization signal frequency, and the above oscillator. and an automatic frequency control circuit for matching the phase of the output of the delay circuit with the phase of the output of the delay circuit, and the output of the synchronization signal generation circuit and the output of the oscillator are ANDed to determine whether the composite video signal is a regular video signal. 1. A video signal discriminating circuit comprising: a logic circuit that outputs a discriminating signal for determining whether