JPS59154821A - Circuit for transmitting initializing signal - Google Patents

Abstract

PURPOSE:To attain sure operation by detecting a voltage when a power supply voltage is its minimum permissible voltage or below at the rising of the power supply voltage so as to zero the initialized signal voltage and making the rising voltage pass through the permissible voltage lower than the signal voltage. CONSTITUTION:The power supply voltage Vcc is inputted to an inverting input of a comparator 2a and a reference voltage VREF is inputted to a non-inverting input. Further, the power supply voltage Vcc is inputted to an integration circuit having a time constant comprising a resistor R3 and a capacitor C, its output is inputted to an inverting input of a comparator 2b and the power supply voltage Vcc is inputted to a non-inverting input. Then, the comparator 2b detects a delayed voltage and an NOT signal of the output of the comparator 2b is inputted in parallel with the inverting input of the comparator 2b so as to attain initialization. Further, the output of the comparators 2a, 2b is inputted to an NOR circuit, and when a voltage higher than the reference voltage is detected at the rising of the power supply, the initializing signal is transmitted with the time constant of the integration circuit, and when a lower voltage is detected, the initializing signal is cancelled immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION lal Technical Field of the Invention The present invention relates to an improvement in initialization signal sending means in a logic circuit.

Background of lbl technology Logic circuits have traditionally been made of relays, vacuum tubes, etc., but in recent years, most of them have been made of semiconductors. Logic circuits are basically Cf
Combinational circuit units (gates) like NAND and NOR circuits and registers and latches.

It consists of a large number of interconnected sequential circuit units such as flip-flop circuits. In addition, functionally, logic circuits are roughly divided into data blocks and control blocks, and data processors are used to transfer data between various registers, latches, flip-flop circuits (FF), etc. used to hold data. The control block is the transfer sequence within the data block.

Various registers and latches that control row sequences, etc.

Consists of FF group. In this way, logic circuits are composed of many sequential circuit units for various purposes and gates inserted around the sequential circuit units as necessary, but in these sequential circuits, the gates uniquely respond to input signals. While the logic of the output signal is determined, the sequential circuit has two stable logics, 1 or 0, for the output signal in response to the input signal number, like an FF. Therefore, with the exception of sequential circuits that are particularly equipped with initialization means, normally the logic operation period is first started, and after a certain period of time after the supply voltage of the logic circuit reaches a predetermined operating voltage, all sequential circuits are brought into a preset logic state. It is necessary to apply a reset signal to reset.

(cl Prior Art and Problems Conventional logic circuits have a simple circuit as shown in FIG. 1, which is a block diagram showing the initialization signal sending circuit of a conventional logic circuit. FIG. 2 [al t ('l + (cl.
shows that time 1,000 yards. In the figure, 1 is a logic circuit such as a microprocessor (MPU), C is a capacitor, R is a resistor, and D is a diode. C and R
6 constitutes an integrator circuit, and the supply voltage V of DGJMPUL is
This is for rapid discharge when CC is disconnected. According to this configuration, when VCC rises, the initialization signal voltage VR applied to the reset terminal of MPU 1 changes as shown in FIG.
The fixed time t l ”'-' when the minimum allowable voltage w plane is reached
2 = Sufficient spare time for 'II, e.g. several tens of m5~
After 100m5, VR is the threshold value of logic “L” Vs, for example, V
Standard value of CC5. MPUI reaches 2.4V against OV
is reset and normal operation can begin. On the other hand, V
At the falling edge when cc is disconnected, VR
Although the forward voltage VF of D also drops by 0.6 V, the result follows a voltage trajectory higher than that of VF by 0.6 V.

Therefore, the minimum and maximum allowable voltages of VCC Vmln, Vmax
MPUI whose normal operation is guaranteed only within the range of V
In a region where CC is lower than Vmin, an error occurs or a runaway occurs. For this reason, normally, although not shown in the drawings, VCC is monitored on the VCC power supply side, and when a situation occurs where the voltage drops below Vmin, for example, a low voltage detection means is provided to send out an alarm and disconnect VCC. Control means are provided to stop the operation. Vcc is below Vmin and VR is Vs
For example, if it becomes O when going below the
When VCC is increased by l, it is applied when the sparrow rises again from O and reaches Vs, so MPU 1
There is no problem with the operation of the VCC as shown in Figure 2 (cl).
If VR is restored without falling below Vs due to a momentary interruption of the commercial power supply, etc., and is not controlled by low voltage detection means, which is another VCC detection means, for example, Vcc is temporarily reduced to Vmi.
Since the time period t4, which is less than n, has elapsed, the MPU 1 may continue to operate without recovering due to an error or runaway. In such an abnormal situation, the operator needs to turn off the power, turn it on again, and redo the data processing or other work, but it is difficult for the operator to recognize the abnormal situation, and the redo work is cumbersome, so it is often overlooked. normal work is lost.

idl Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by resetting the MPU1 by exceeding Vs as an initial signal for a certain period of time, and detecting that VCC has fallen below Vmin when Vcc rises. and a means for quickly resetting VR to O when VCC continues to rise and exceeding Vmin, and a means for applying an initialization signal by configuring VR to be passed from a voltage lower than VS whenever VCC rises and exceeds Vmin. This is what I am trying to do.

(el) Structure of the Invention The object of the present invention is to provide a power on/off system for a logic circuit having a sequential circuit unit by inputting the supply voltage of the logic circuit to an inverting terminal, inputting a reference voltage to a non-inverting terminal, and outputting a comparison signal thereof. means for detecting an interlocked voltage by a first operational amplifier, the power supply voltage is input to an inverting terminal via an integrating circuit having an arbitrary time constant, the reference voltage is input to a non-inverting terminal, and a comparison signal thereof is obtained. Means for detecting the delayed voltage outputted by the second operational amplifier, a negation signal of the output of the motion type voltage detecting means is input in parallel to the inverting terminal of the delayed voltage detecting means, and the detecting means is first stamped. The gate means is provided with a gate means for obtaining a negative OR, and when a voltage exceeding the reference voltage is detected at the rise of the supply voltage of the logic circuit, the gate means performs an initialization of the logic circuit at a timing determined by the time constant of the integrating circuit. This can be achieved by providing an initialization signal sending circuit for a logic circuit, which is characterized in that it sends out an initialization signal and immediately erases the initialization signal when a lower voltage is detected.

(fl Embodiment of the Invention An embodiment of the invention will be explained below with reference to the drawings. FIG. 3 is a block diagram of an initialization signal sending circuit in an embodiment of the invention, and FIG. 4 1al, (bl is the time chart. In the figure, 1 is the same logic circuit as before, such as a microprocessor (MPU), 2a is the first operational amplifier, 2b is the second operational amplifier, NOR is the NOR circuit, R, , R ,,R.

is a resistor and C is a capacitor. In addition to the normal output OI, the operational amplifier 2a has its negative output 0. A reference voltage VRFtF, which is the same voltage as the "1" threshold VS in the logic circuit, is input to the non-inverting terminal number, and Vc CX R is input by resistors R8 and R8.

/ RI 10, = Vk voltage is set here to a value equal to the lower limit permissible value Vmin of the supply power voltage VCC of the MPU1. Therefore, the output 01 of the operational amplifier 2a is a high level "1" when Vk < Vugp, which is input to the non-inverting terminal.
When Vk>VasF, it operates as a comparator that outputs a low velocity of 0''.Similarly, the operational amplifier 2b inputs the reference voltage VREF to the non-inverting terminal, and the voltage Vt in the integrating circuit formed by the resistor IRm and the capacitor C is input to the operational amplifier 2b. is input to the inverting terminal and Vl (“l” for VREF, Vt) VRE
When it is F, it operates as a comparator that sends out 10#. However, since the negative output O7 of the operational amplifier 2a is applied in parallel to the non-inverting terminal voltage Vt via the resistor R6, when the operational amplifier 2a is Vk<VREF, the applied voltage Vt increases by 10''. Therefore, the rising special number of VCC is the same as the conventional one as shown in the time chart of FIG. + l Vl starts to rise from the timing when Vk intersects with Vmln, which is transposed in Operation 7- The output of amplifier 2b is Vt) Timing tl+ of VRgp
As a result, the 01 output of the operational amplifier 2a and the output of the operational amplifier 26 are applied to the input of the NOR, so at timing t1, both are @1''''l.
At ``, the output of NOR is 10'', the time domain of timing 1° is ``0'', 11'', and at the point where Vt intersects VREF, ``O'''''0# is obtained, so the output VRR of NOR is 0.
→Transferred to 1 and an MPU initialization signal is sent. When VCC falls, which was a problem in the past, as shown in Figure 4 (bl), when VCC starts to fall and its voltage reaches h, the 01 output of operational amplifier 2a changes to O-+1 and the output of NOR. When VRR is shifted from 1 to O, the co-reactive O7 output changes from l to 0.
The voltage at the inverting terminal of the operational amplifier 2b is forcibly lowered. Therefore, Vt rapidly approaches zero. Therefore, even if there is an instantaneous interruption similar to that shown in Fig. 2, which may conventionally cause errors, VRR is temporarily set to 0 and
Vt starts to rise from the point when CC rises and crosses ①, and retransmission of VRR is suppressed until t@ at the point where Vt crosses VRBF. conversion signal VR
Since VRR is sent out after a certain period of time determined by the time constant of resistor R8 and capacitor C, which constitute the integrating circuit, from the point when R is suppressed and MPUI exceeds Vmin, which enables operation, VRR is sent out, so there is no error in the operation of the logic circuit as in the conventional case. This provides an initialization signal sending circuit that does not cause the occurrence of.

Although the first operational amplifier 2a has two positive and negative outputs, it goes without saying that the same implementation can be achieved by adding a negative circuit to one output similar to the second operational amplifier 2b.

tgl As described in detail, according to the present invention, the initialization signal is always suppressed whenever the supply voltage of the logic circuit falls below the lower limit tolerance, and a certain period of time after the supply voltage exceeds the lower limit tolerance. Since the initialization signal is sent and the logic circuit is reset, the supply power supply voltage does not go through the region below the lower limit tolerance and return to the lower limit tolerance or higher without being reset again, unlike in the conventional case. Therefore, it is useful because the operator no longer has to worry about data errors that occur in logic circuits due to a drop in supply voltage.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a conventional initialization signal sending circuit of a logic circuit, Fig. 2 is a time chart thereof, and Fig. 3 is an initialization signal sending circuit according to an embodiment of the present invention. The configuration diagram and FIG. 4(a). (bl shows the time chart. In the figure, 1 is a microprocessor (MPU), 2a and 2b are operational amplifiers, NOR is a NOR circuit, Ro, R, , g, , R3 ，
R, is a resistor and C is a capacitor. 11- Mine 1 Zuyu Pass +71 (

Claims (1)

[Claims] In a power on/off system for a logic circuit having a sequential circuit unit, an interlocking type using a first operational amplifier that manually inputs the supply voltage of the logic circuit to an inverting terminal, inputs a reference voltage to a non-inverting terminal, and outputs a comparison signal thereof. means for detecting the voltage of , a delay by a second operational amplifier that inputs the power supply voltage to the inverting terminal via an integrating circuit having an arbitrary time constant, inputs the reference voltage to the non-inverting terminal, and outputs the comparison signal. means for detecting the voltage of the type, means for initializing the detection means by inputting in parallel the negation signal of the output of the interlocking voltage detection means to the inverting terminal of the delay type voltage detection means, and means for initializing the detection means; The gate means is provided with a gate means for obtaining a negative disjunction by applying a voltage to the logic circuit, and the gate means sends out an initialization signal for integration when a voltage higher than the reference voltage is detected at the rise of the supply voltage of the logic circuit. An initialization signal sending circuit for a logic circuit, wherein the initialization signal is immediately erased when a lower phase voltage is detected.