JPS59154039A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59154039A
JPS59154039A JP2705183A JP2705183A JPS59154039A JP S59154039 A JPS59154039 A JP S59154039A JP 2705183 A JP2705183 A JP 2705183A JP 2705183 A JP2705183 A JP 2705183A JP S59154039 A JPS59154039 A JP S59154039A
Authority
JP
Japan
Prior art keywords
type
electrode
layer
insulating film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2705183A
Other languages
Japanese (ja)
Inventor
Masao Kobayashi
正男 小林
Hiroshi Takano
紘 高野
Ryozo Furukawa
古川 量三
Takeshi Kamijo
健 上條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2705183A priority Critical patent/JPS59154039A/en
Publication of JPS59154039A publication Critical patent/JPS59154039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize double-layer wiring on a flat insulating film by providing a groove at the surface of semiconductor substrate, burying a first electrode wiring layer in such a groove and forming an insulating film so thate the semiconductor surface becomes flat and to improve yield by eliminating short-circuitting of wirings between layers. CONSTITUTION:An N type layer 2 is formed on a P type substrate 1 and a P type diffused layer 3 on such N layer 2. An etching groove 9 for forming electrode is formed by etching to the N type layer 2, an N type electrode 4 is formed to the etching groove 9 by the lift-off method of the vacuum deposition method, an insulating film 5 is formed by the CVD method, a through hole 7 is bored by the rithography and a P type electrode 6 is formed by the vacuum-deposition method. A semiconductor device thus manufactured allows the P type electrode 6 as the second electrode to be formed on the flat insulating film by burying the N type electrode 4 as the first layer electrode at the surface of substrate. Accordingly, disconnection of electrode wiring does not occur at the stepped region and the yield can be improved.

Description

【発明の詳細な説明】 (技術分野) この発明は、段差のない2層配線を得ることができるよ
うにし・た半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device that makes it possible to obtain two-layer wiring without steps.

(従来技術) 従来の半導体装置は第1図(a)゛〜第1図(c)に示
すように製造されてお9、この第1図(a)〜第1図(
C)において、1はP型基板(またはN型)、2はN型
層(またはP型層)、3はP型拡散層(またはN型拡散
層)、4はN型電極(またはP型電極)、5は絶縁膜、
6はP型電極(またはN型電極)、7はスルーホール、
8は絶縁膜の段差である。
(Prior Art) A conventional semiconductor device is manufactured as shown in FIGS. 1(a) to 1(c).
In C), 1 is a P-type substrate (or N-type), 2 is an N-type layer (or P-type layer), 3 is a P-type diffusion layer (or N-type diffusion layer), and 4 is an N-type electrode (or P-type electrode), 5 is an insulating film,
6 is a P-type electrode (or N-type electrode), 7 is a through hole,
8 is a step in the insulating film.

次に、この半導体装置の製造方法について述べる。まず
、第1図(a)に示すごとくP型基板1にN型層2を形
成する。次に、N型層2にP型拡散層3を拡散し、N型
層2にN゛型電極4を真空蒸着法により形成する。
Next, a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 1(a), an N-type layer 2 is formed on a P-type substrate 1. Next, a P-type diffusion layer 3 is diffused into the N-type layer 2, and an N'-type electrode 4 is formed on the N-type layer 2 by vacuum evaporation.

次に、第1図(b)に示すように、P型基板1の表面に
絶縁膜5をCVD法により育成し、公知のリングラフィ
によシ絶縁膜のスルーホール7を作製する。
Next, as shown in FIG. 1(b), an insulating film 5 is grown on the surface of the P-type substrate 1 by CVD, and through-holes 7 in the insulating film are formed by known phosphorography.

この基板を第1図(c)に示すごとく、真空蒸着法によ
り、P型電極6を形成する。この際、絶縁膜5の段差8
によりP型電極6が段切れを生じたり、N型電極4とP
型電極6がショートしたシして歩留9の低下を生じる欠
点があった。
As shown in FIG. 1(c), a P-type electrode 6 is formed on this substrate by vacuum evaporation. At this time, the step 8 of the insulating film 5
This may cause the P-type electrode 6 to break off, or the N-type electrode 4 and P
There was a drawback that the mold electrode 6 was short-circuited, resulting in a decrease in yield of 9.

(発明の目的) この発明は、上記従来の欠点を除去するためになされた
もので、2層目の電極配線を平担な絶縁膜上に配線でき
るとともに、2層以上の配線を必要とする半導体装置に
も利用でき、しかも、各層間の電極のショート防止、歩
留りの向上を期することのできる半導体装置の製造方法
を提供することを目的とする。
(Purpose of the Invention) This invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and allows the second layer of electrode wiring to be wired on a flat insulating film, while also requiring two or more layers of wiring. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can also be used for semiconductor devices and can prevent short circuits between electrodes between layers and improve yield.

(発明の構成) この発明の半導体装置の製造方法は、半導体基板表面を
エツチングして溝を形成し、この溝に第1層の電極を埋
め込み、この第1層目の電極形成後の半導体基板表面が
平担になるように絶縁膜を形成するようにしたものであ
る。
(Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention includes etching the surface of a semiconductor substrate to form a groove, embedding a first layer of electrodes in the grooves, and etching the semiconductor device after forming the first layer of electrodes. The insulating film is formed so that the surface is flat.

(実施例) 以下、この発明の半導体装置の実施例について図面に基
づき説明する。第2図(a)ないし第2図(d)はその
一実施例を説明するための工程説明図である。この第2
図(a)〜第2図(d)において、第1図(a)〜第1
図(c)と同一部分には同一符号を付して述べる。
(Embodiments) Hereinafter, embodiments of the semiconductor device of the present invention will be described based on the drawings. FIG. 2(a) to FIG. 2(d) are process explanatory diagrams for explaining one embodiment thereof. This second
In Figures (a) to 2(d), Figures 1(a) to 1
The same parts as in Figure (c) will be described with the same reference numerals.

まず、第2図(a)に示すように、P型基板1(または
N型)にN型層2(またはP型層)を形成し、そのN型
層2にP型拡散層3(またはN型拡散層)を作る。
First, as shown in FIG. 2(a), an N-type layer 2 (or P-type layer) is formed on a P-type substrate 1 (or N-type), and a P-type diffusion layer 3 (or (N-type diffusion layer).

次に、N型層2に電極形成用のエツチング溝9をエツチ
ングにより作成し、第2図(b)に示すごとく、エツチ
ング溝9に真空蒸着法によりN型電極4(またはP型電
極)をリフトオフ法により作成し、第、2図(c)に示
すよう°に゛絶縁膜5をCVD法により育成し、リング
ラフィによりスルーホール7をあけ、第2図(d)に示
すごとくP型電極6(またはN型電極)を真空蒸着法に
より形成する。
Next, an etching groove 9 for forming an electrode is created in the N-type layer 2 by etching, and an N-type electrode 4 (or a P-type electrode) is formed in the etching groove 9 by vacuum deposition, as shown in FIG. 2(b). As shown in FIG. 2(c), an insulating film 5 was grown using the CVD method, and a through hole 7 was formed using phosphorography to form a P-type electrode as shown in FIG. 2(d). 6 (or an N-type electrode) by vacuum evaporation.

このようにして製造した半導体装置は1層目の電極とし
てのN型電極4を基板表面に埋め込むことにより2層目
の電極としてのP型電極6を平担な絶縁膜上に形成でき
るため、電極配線の段切れが生じることなく、歩留シが
向上する。
In the semiconductor device manufactured in this way, by embedding the N-type electrode 4 as the first-layer electrode into the substrate surface, the P-type electrode 6 as the second-layer electrode can be formed on a flat insulating film. Yield is improved without causing disconnection of electrode wiring.

以上説明したように、この実施例では、2層電極のうち
一方の電極が半導体基板表面に埋め込まれているため2
層目の電極形成時に平担な絶縁膜上に配線を行なうため
絶縁膜の段差による段切れが防止でき、歩留9が向上で
きる。
As explained above, in this embodiment, one of the two-layer electrodes is embedded in the surface of the semiconductor substrate, so
Since wiring is performed on a flat insulating film when forming layered electrodes, breakage due to step differences in the insulating film can be prevented, and the yield rate can be improved.

第3図は第1の実施例で説明した製造方法で製造したG
aAsPのLEDディスプレイの斜視図で、10はP型
GaAsP基板、11はN型層、12はP型層、13は
N型電極、14は絶縁膜、15はP型電極を示す。
Figure 3 shows a G manufactured by the manufacturing method explained in the first example.
This is a perspective view of an aAsP LED display, and 10 is a P-type GaAsP substrate, 11 is an N-type layer, 12 is a P-type layer, 13 is an N-type electrode, 14 is an insulating film, and 15 is a P-type electrode.

まず、GaAsP基板1oにN型層11をイオン注入法
などを用いて形成し、さらに、N型層11に選択拡散法
を用いてP型層12を拡散する。
First, an N-type layer 11 is formed on a GaAsP substrate 1o using an ion implantation method, and then a P-type layer 12 is diffused into the N-type layer 11 using a selective diffusion method.

次いで、N型層11にエツチング溝9をN型電極13の
厚さだけエツチングし、このエツチング溝9に真空蒸着
法にょシミ極を蒸着し、リフトオフ法を用いてN型電極
13を作る。
Next, an etching groove 9 is etched in the N-type layer 11 by the thickness of the N-type electrode 13, a stain electrode is deposited in the etching groove 9 using a vacuum evaporation method, and an N-type electrode 13 is formed using a lift-off method.

これにより、基板表面はN型電極13を形成した後に平
担となっている。
As a result, the surface of the substrate becomes flat after the N-type electrode 13 is formed.

次に、基板表面にCVD法を用いてSin、などの絶縁
膜14を育成し、P型層12にスルーポール7をリング
ラフィにて作成し、真空蒸着法およびエツチングにてP
型電極15を配線する。
Next, an insulating film 14 such as Sin is grown on the substrate surface using the CVD method, through poles 7 are created on the P-type layer 12 using phosphorography, and P is etched using a vacuum evaporation method and etching.
Wire the mold electrode 15.

このように、N型電極13を基板表面に埋め込むことに
より、2層目の電極配線を行なうとき、平担な絶縁膜上
に形成できるため電極の配線切れを防止でき、歩留9が
向上できる。
In this way, by embedding the N-type electrode 13 in the substrate surface, when the second layer of electrode wiring is performed, it can be formed on a flat insulating film, which prevents the electrode wiring from breaking and improves the yield. .

(発明の効果) 以上のように、この発明の半導体装置の製造方法によれ
ば、半導体基板表面に溝を設け、この溝゛に第1層目の
電極配線を埋め込んだ後、半導体表面が平担になるよう
に絶縁膜を形成するようにしたので、2層配線を行なう
際2層目の電極配線を平担な絶縁膜上に配線できる利点
があり、2層以上の配線を必要とする半導体装置におい
ても利用することができるとともに、各層間の配線のシ
ョートがなくなり、歩留りの向上を期することができる
(Effects of the Invention) As described above, according to the method for manufacturing a semiconductor device of the present invention, a groove is provided in the surface of a semiconductor substrate, and after the first layer of electrode wiring is embedded in the groove, the semiconductor surface is flat. Since the insulating film is formed to act as a support, there is an advantage that when performing two-layer wiring, the second layer of electrode wiring can be wired on a flat insulating film, which eliminates the need for two or more layers of wiring. It can also be used in semiconductor devices, eliminates short circuits between layers, and improves yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)ないし第1図(c)はそれぞれ従来の半導
体装置の製造方法を説明するための工程説明図、第2図
(a)ないし第2図(d)はそれぞれこの発明の半導体
装置の一実施例の工程説明図、第3図はこの発明の半導
体装置の、製造方法によシ製造されたGaAsPのLE
Dディスプレイの斜視図である。 1・・・P型基板、2・・・N型層、3・・・P型拡散
層、4・・・N型電極、14・・・絶縁膜、15・・・
P型電極、7・・・スルーホール、8・・・絶縁膜の段
差、9・・・エツチング溝、10・・・P型GaAsP
基板、11・・・N型層、12・・・P型層、13・・
・N型電極。 第1図    第2区 第3図 71+ 1215 10  ソ
FIGS. 1(a) to 1(c) are process explanatory diagrams for explaining a conventional method of manufacturing a semiconductor device, and FIGS. 2(a) to 2(d) are semiconductors of the present invention, respectively. FIG. 3 is a process explanatory diagram of an embodiment of the device, and FIG. 3 shows a GaAsP LE manufactured by the manufacturing method of the semiconductor device of the present invention.
It is a perspective view of D display. DESCRIPTION OF SYMBOLS 1... P type substrate, 2... N type layer, 3... P type diffusion layer, 4... N type electrode, 14... Insulating film, 15...
P-type electrode, 7... Through hole, 8... Insulating film step, 9... Etching groove, 10... P-type GaAsP
Substrate, 11... N-type layer, 12... P-type layer, 13...
・N-type electrode. Figure 1 District 2 Figure 3 71+ 1215 10 So

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面にエツチング溝を形成し、このエツチン
グ溝に第1層の電極を埋め込んで配線を行ない、この第
1層の電極の配線を行なった後に半導体基板表面(2平
担な絶縁膜を形成することを特徴とする半導体装置の製
造方法。
An etching groove is formed on the surface of the semiconductor substrate, a first layer electrode is embedded in this etching groove and wiring is performed, and after wiring the first layer electrode, the semiconductor substrate surface (two flat insulating films are formed). A method for manufacturing a semiconductor device, characterized in that:
JP2705183A 1983-02-22 1983-02-22 Manufacture of semiconductor device Pending JPS59154039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2705183A JPS59154039A (en) 1983-02-22 1983-02-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2705183A JPS59154039A (en) 1983-02-22 1983-02-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59154039A true JPS59154039A (en) 1984-09-03

Family

ID=12210270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2705183A Pending JPS59154039A (en) 1983-02-22 1983-02-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59154039A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929779A (en) * 1972-07-18 1974-03-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929779A (en) * 1972-07-18 1974-03-16

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