JPS5915383B2 - Mounting equipment for semiconductor integrated circuits - Google Patents

Mounting equipment for semiconductor integrated circuits

Info

Publication number
JPS5915383B2
JPS5915383B2 JP53134162A JP13416278A JPS5915383B2 JP S5915383 B2 JPS5915383 B2 JP S5915383B2 JP 53134162 A JP53134162 A JP 53134162A JP 13416278 A JP13416278 A JP 13416278A JP S5915383 B2 JPS5915383 B2 JP S5915383B2
Authority
JP
Japan
Prior art keywords
semiconductor integrated
chip
integrated circuit
lower surfaces
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53134162A
Other languages
Japanese (ja)
Other versions
JPS5561045A (en
Inventor
宗生 八田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53134162A priority Critical patent/JPS5915383B2/en
Publication of JPS5561045A publication Critical patent/JPS5561045A/en
Publication of JPS5915383B2 publication Critical patent/JPS5915383B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】 この発明は半導体集積回路用実装化装置に関し、特に半
導体集積回路チップの高密度実装に適した装置に係わる
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a packaging device for semiconductor integrated circuits, and more particularly to a device suitable for high-density packaging of semiconductor integrated circuit chips.

従来の半導体集積回路用実装化装置の一例を第１図に示
してある。An example of a conventional semiconductor integrated circuit mounting apparatus is shown in FIG.

この第１図において、絶縁基５ 板１は図示省略した実
装プリント基板に配設される外部配線パターンのスルホ
ールに挿入接続される各端子脚２を外側部に突設させて
あり、この絶縁基板１の板面に凹設したチップ保持部３
には、内周に沿わせて内側段部４を形成してある。そし
１０てまた前記絶縁基板１の内部に配設されて、前記各
端子脚２に接続された内部配線パターンは、その該当す
る各内部端子５を前記内側段部４に取出して位置させて
ある。さらに半導体集積回路チップ６は前記チップ保持
部３内に、適宜鑞付けなど１５によシ固定して搭載され
ており、その外周部に形成させた各チップ電極７と前記
各内部端子５とを、相互に金属細線８により電気的に接
続させた上で、この半導体集積回路チップ６を含むチッ
プ保持部３を、蓋板９によつて被蓋封止させ、これによ
つ２０て回路ブロックパッケージ１０としたものである
。しかし乍らこのような構成による従来の半導体集積回
路用実装化装置では、絶縁基板１の板面に凹設したチッ
プ保持部３に内側段部４を形成させ、この内側段部４に
対して単に１個の半導体集積回２５路チップ６を搭載さ
せるだけであるため、複数個の半導体集積回路チップを
実装させる場合には、必然的に同一構造の回路ブロック
パッケージ１０を複数個必要とし、実装プリント基板へ
のチップ１個当Ｄの実装面積が増加して、高密度実装を
行３０うことができず、かつ１つの回路ブロックパッケ
ージには１個のチップによる機能しか与えられなくて、
機能の多様化を求め得られないという不都合があつた。
この発明は従来のこのような欠点を改善するたあ め、
１つの回路ブロックパッケージ内に２個の半導体集積回
路チップを搭載し得るようにしたものであつて、その要
旨とするところはパッケージを１ク３−構成する絶縁基
板の上、下両面に各々半導体集積回路チツプを搭載させ
るようにしたことである。In this FIG. 1, an insulating board 5 and a board 1 have respective terminal legs 2 protruding from the outside to be inserted and connected to through holes of an external wiring pattern arranged on a mounted printed circuit board (not shown), and this insulating board Chip holding part 3 recessed in the plate surface of 1
An inner step portion 4 is formed along the inner periphery. 10 Furthermore, the internal wiring pattern disposed inside the insulating substrate 1 and connected to each of the terminal legs 2 has its corresponding internal terminal 5 taken out and positioned on the inner step 4. . Further, the semiconductor integrated circuit chip 6 is mounted in the chip holder 3 in a fixed manner 15 by brazing or the like as appropriate, and each chip electrode 7 formed on the outer periphery and each of the internal terminals 5 are connected to each other. After being electrically connected to each other by thin metal wires 8, the chip holder 3 containing the semiconductor integrated circuit chip 6 is covered and sealed with a cover plate 9, thereby forming a circuit block 20. This is package 10. However, in the conventional semiconductor integrated circuit mounting apparatus having such a configuration, an inner step 4 is formed in the chip holding section 3 recessed in the plate surface of the insulating substrate 1, and the inner step 4 is Since one 25-way semiconductor integrated circuit chip 6 is simply mounted, when mounting a plurality of semiconductor integrated circuit chips, a plurality of circuit block packages 10 of the same structure are inevitably required, and the mounting The mounting area per chip D on the printed circuit board increases, making it impossible to perform high-density mounting, and one circuit block package can only be given the function of one chip.
There was an inconvenience in that it was not possible to obtain diversification of functions.
This invention aims to improve these conventional drawbacks,
It is designed to allow two semiconductor integrated circuit chips to be mounted in one circuit block package. The idea was to install an integrated circuit chip.

以下この発明に係わる半導体集積回路用実装化装置の一
実施例につき、第２図を参照して詳細に説明する。第２
図はこの実施例装置の概要を示す断面図であり、この第
２図に釦いて、前記従来例と同様に各端子脚１２を外側
部に突設させた絶縁基板１１には、上、下両板面に上面
訃よび下面のチツプ保持部１３ａ，１３ｂを凹設させ、
かつこの両チツプ保持部１３ａ，１３ｂ内に、各々内周
に沿わせて上面卦よび下面の内側段部１４ａ，１４ｂを
形成させると共に、基板内部に配設されて、前記各端子
脚１２に接続された内部配線パターンからは、該当する
各内部端子を上面および下面の内部端子１５ａ，１５ｂ
に区分して、前記上面卦よび下面の内側段部１４ａ，１
４ｂに取出して位置させてある。Hereinafter, one embodiment of the semiconductor integrated circuit mounting apparatus according to the present invention will be described in detail with reference to FIG. Second
The figure is a cross-sectional view showing the outline of the apparatus of this embodiment, and as shown in FIG. An upper surface and a lower chip holding portion 13a, 13b are recessed on both board surfaces,
In addition, inner step portions 14a and 14b on the upper and lower surfaces are formed along the inner periphery of both chip holding portions 13a and 13b, respectively, and are disposed inside the board and connected to each of the terminal legs 12. From the internal wiring pattern, each corresponding internal terminal is connected to the internal terminals 15a and 15b on the top and bottom surfaces.
The inner step portions 14a, 1 of the upper surface and lower surface are divided into
It is taken out and placed in 4b.

しかして前記上面卦よび下面のチツプ保持部１３ａ，１
３ｂ内には、各別２個、こ＼では上面卦よび下面の半導
体集積回路チツプ１６ａ，１６ｂを、適宜に鑞付けなど
により固定して搭載させると共に、両半導体集積回路チ
ツブ１６ａ，１６ｂの外周部に形成させた上面｝よび下
面の各チツプ電極１７ａ，１７ｂを、前記した対応する
上面卦よび下面の各内部端子１５ａｐ１５ｂに・各々上
面訃よび下面の金属細線１８ａ，１８ｂにより電気的に
接続させた上で、さらにこれらの上面の半導体集積回路
チツプ１６ａを含む上面のチツプ保持部１３ａ，｝よび
下面の半導体集積回路チツプ１６ｂを含む下面のチツブ
保持部１３ｂの各々を、各別に上面｝よび下面の蓋板１
９ａ，１９ｂにより被蓋封止させ、これによつて回路ブ
ロツクパツケージ、すなわち、上、下面各１個、合計２
個の半導体集積回路チツプ１６ａ，１６ｂを同一絶縁基
板１１内に搭載させた回路ブロツクパツケージ２０とし
たものである。Therefore, the chip holding portions 13a, 1 on the upper surface and the lower surface are
Two separate semiconductor integrated circuit chips 16a, 16b, one on the top surface and the other on the bottom surface, are mounted in each of the chips 3b, fixed by brazing or the like as appropriate, and the outer peripheries of both semiconductor integrated circuit chips 16a, 16b are mounted. The chip electrodes 17a and 17b formed on the top surface and the bottom surface are electrically connected to the corresponding internal terminals 15ap15b on the top surface and the bottom surface, respectively, by thin metal wires 18a and 18b on the top surface and the bottom surface, respectively. In addition, each of the upper chip holding portion 13a, } containing the semiconductor integrated circuit chip 16a on the upper surface and the lower chip holding portion 13b containing the semiconductor integrated circuit chip 16b on the lower surface is separately separated from the upper surface} and the lower surface. cover plate 1
9a and 19b, thereby forming a circuit block package, one each on the upper and lower sides, totaling 2 circuit blocks.
The circuit block package 20 has two semiconductor integrated circuit chips 16a and 16b mounted on the same insulating substrate 11.

従つてこの実施例構成による半導体集積回路用実装化装
置では、１個の絶縁基板１１の上、下両面にチツプ保持
部１３ａ，１３ｂを凹設させ、これらの両チツプ保持部
１３ａ，１３ｂ内に各別２個の半導体集積回路チツプ１
６ａ．１６ｂを搭載させるようにしたから、１つの回路
ブロツクバツケージ２Ｑ．に２個の半導体集積回路チツ
プ１６ａ，１６ｂを組込みことができて、実装密度を倍
増し得られ、ひいては実装プリント基板へのチツブ１個
当ｂの実装面積を半減でき、これによつて実装空間の有
効利用が可能となう、併せて１つの回路プロツクバツケ
ージｌ（Ｉに、２個のチツプによる各別の機能を得て、
結局、高密度かつ多機能な実装を行えるのである。Therefore, in the semiconductor integrated circuit mounting apparatus having the structure of this embodiment, the chip holding parts 13a and 13b are recessed on both the upper and lower surfaces of one insulating substrate 11, and the chip holding parts 13a and 13b are provided with recesses. 2 separate semiconductor integrated circuit chips 1
6a. 16b, one circuit block baggage 2Q. It is possible to incorporate two semiconductor integrated circuit chips 16a and 16b into the board, doubling the packaging density, and halving the mounting area per chip b on the printed circuit board, thereby saving mounting space. In addition, it is possible to effectively utilize the circuit block bag l (I) by obtaining different functions from two chips,
In the end, it is possible to implement high-density and multifunctional implementation.

な卦前記実施例は、デイアルインラインパツケージを構
成する絶縁基板の上、下両面に各々半導体寮積回路チツ
プを搭載させ、かつワイヤボンデイング法によりその接
続をなした場合であるが、この発明はこの型式に限られ
るものでなく、広くその他のフラツトパツケージあるい
はリードレスパツケージ、もしくはマザーボートを使用
する場合にも適用できることは勿論である。In the above embodiment, semiconductor integrated circuit chips are mounted on the upper and lower surfaces of the insulating substrate constituting the daily in-line package, and the connections are made by wire bonding. Of course, the present invention is not limited to this type, and can be widely applied to other flat packages, leadless packages, or motherboards.

以上詳述したようにこの発明によるときは、絶縁基板の
上、下両面にチツグ保持部を凹設させ、両チツブ保持部
内に各別２個の半導体集積回路チツプを搭載し得るよう
にしたから、１つの回路プロツクパツケージに２個の半
導体集積回路チッＺ゜を組込むことができて、高密度、
多機能実装を実現でき、しかも構成が簡単で容易かつ安
価に実施できるものである。As detailed above, according to the present invention, the chip holders are recessed on both the upper and lower surfaces of the insulating substrate, and two separate semiconductor integrated circuit chips can be mounted in each of the chip holders. , two semiconductor integrated circuit chips can be incorporated into one circuit block package, resulting in high density,
It is possible to realize multi-functional implementation, and the configuration is simple and can be implemented easily and inexpensively.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例による半導体集積回路用実装化装置の概
要を示す断面図、第２図はこの発明に係わる半導体集積
回路用実装化装置の一実施例による概要を示す断面図で
ある。 １１゜゜゜゜゜゜絶縁基板、１２・・・・・・端子脚、
１３・・・・・・チツプ保持部、１４ａ，１４ｂ・・・
・・・上面、下面の内側段部、１５ａ，１５ｂ・・・・
・・上面、下面の内部端子、１６ａ，１６ｂ・・・・・
・上面、下面の半導体集積回路チツプ、１７ａ，１７ｂ
・・・・・・上面、下面のチツプ電極、１８ａ，１８ｂ
・・・・・・上面、下面の金属細線、１９ａ，１９ｂ・
・・・・・上面、下面の蓋板、２０・・・・・・回路ブ
ロツクパツケージ。FIG. 1 is a sectional view showing an outline of a conventional semiconductor integrated circuit mounting apparatus, and FIG. 2 is a sectional view showing an outline of an embodiment of a semiconductor integrated circuit mounting apparatus according to the present invention. 11゜゜゜゜゜゜゜Insulating board, 12...Terminal leg,
13... Chip holding section, 14a, 14b...
... Inner step portions of upper and lower surfaces, 15a, 15b...
・Internal terminals on the top and bottom surfaces, 16a, 16b...
・Semiconductor integrated circuit chips on the top and bottom surfaces, 17a, 17b
...Tip electrodes on the top and bottom surfaces, 18a, 18b
・・・・・・Thin metal wires on the top and bottom surfaces, 19a, 19b・
...Top and bottom cover plates, 20...Circuit block package.

Claims (1)

【特許請求の範囲】[Claims] １ 実装プリント基板に挿入接続される各端子脚を外側
部に突設させた絶縁基板を有し、この絶縁基板の上、下
両板面に各々内側段部をもつ上面および下面のチップ保
持部を凹設させると共に、基板内部に配設して前記各端
子に接続される内部配線パターンの、該当する上面およ
び下面の各内部端子を区分して、前記上面および下面の
内側段部に取出して位置させ、また前記上面および下面
のチップ保持部内には、各々上面および下面の半導体集
積回路チップを搭載させて、その上面および下面の各チ
ップ電極と前記上面および下面の各内部端子とを電気的
に接続させ、さらにこれら上面の半導体集積回路チップ
を含む上面のチップ保持部、および下面の半導体集積回
路チップを含む下面のチップ保持部を、各別に各々蓋板
によつて被蓋封止させたことを特徴とする半導体集積回
路用実装化装置。1. It has an insulating board on which each terminal leg to be inserted and connected to the mounted printed circuit board protrudes from the outside, and chip holding parts on the upper and lower surfaces of the insulating board have inner stepped parts on both the upper and lower surfaces of the insulating board, respectively. At the same time, each of the internal terminals on the upper and lower surfaces of the internal wiring pattern arranged inside the board and connected to each of the terminals is divided and taken out to the inner stepped portions of the upper and lower surfaces. The upper and lower semiconductor integrated circuit chips are mounted in the upper and lower chip holders, respectively, and the chip electrodes on the upper and lower surfaces are electrically connected to the internal terminals on the upper and lower surfaces. Furthermore, the upper chip holder containing the semiconductor integrated circuit chip on the upper surface and the lower chip holder containing the semiconductor integrated circuit chip on the lower surface were each separately covered and sealed with a cover plate. A mounting device for semiconductor integrated circuits, characterized in that:
JP53134162A 1978-10-30 1978-10-30 Mounting equipment for semiconductor integrated circuits Expired JPS5915383B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53134162A JPS5915383B2 (en) 1978-10-30 1978-10-30 Mounting equipment for semiconductor integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53134162A JPS5915383B2 (en) 1978-10-30 1978-10-30 Mounting equipment for semiconductor integrated circuits

Publications (2)

Publication Number Publication Date
JPS5561045A JPS5561045A (en) 1980-05-08
JPS5915383B2 true JPS5915383B2 (en) 1984-04-09

Family

ID=15121897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53134162A Expired JPS5915383B2 (en) 1978-10-30 1978-10-30 Mounting equipment for semiconductor integrated circuits

Country Status (1)

Country Link
JP (1) JPS5915383B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780854U (en) * 1980-10-31 1982-05-19
JPS57128994A (en) * 1981-02-02 1982-08-10 Nippon Electric Co Lsi mounting structure
JPS62116440U (en) * 1986-01-14 1987-07-24

Also Published As

Publication number Publication date
JPS5561045A (en) 1980-05-08

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