JPS59153350A - Viterbi decoding circuit - Google Patents

Abstract

PURPOSE:To increase the decoding gain by arranging the results of operation at each ACS circuit into a table and replacing them into a read only memory. CONSTITUTION:Each arithmetic operation in ACS circuits 401a-401n is formed into a table and this table is stored in the read only memory. The received signal and the likelihood before one bit are applied to the memory as an address and the table stored in the memory is read by this address signal to obtain a bus selector signal and a new likelihood.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Viterbi decoding circuit, and is particularly directed to simplifying the circuit structure and realizing a highly accurate Viterbi decoding circuit.

<Background of the invention> What is the Viterbi decoding circuit? In 1971, American A.J.
It was proposed by Mr. arbi, and its purpose is a decoder designed for so-called error correction, which removes disturbances that occur during transmission5. Codes commonly used for error correction can be roughly divided into block codes, block codes, There are two types of conglomeration codes. The Viterbi decoding method is one of the decoding methods for decoding the X convolutional code. Other methods for decoding convolutional codes include threshold decoding and sequential decoding.

Among these decoding methods, the Viterbi post-decoding method has maximum likelihood.
It is known to have the highest error correction ability of any decoding method, and its superiority has already been demonstrated through some practical use in the field of satellite communications.

<Description of Prior Art> (1) Concerning convolutional encoder, an example of a convolutional encoder is shown in FIG. The convolutional encoder shown in this example is constructed from a three-stage not register 101, exclusive OR circuits 102 and 103, and a parallel-to-serial converter 104. An input signal ■ is applied to the input terminal 105 of the first stage of the shift register 101. Exclusive OR circuit 10
2 inputs the signals of each stage of the shift register 101 and outputs the code X+. The exclusive OR circuit 103 inputs the signals of the first stage and the last stage of the shift register 1.01, and outputs the sign X2. Since these codes X1 and X2 are parallel signals, the parallel-to-serial converter 104 performs parallel-to-serial conversion at twice the speed of the input signal
Codes Xi, X which are time-divisionally convolutionally encoded into
2 and transmits the sign q' X l , X 2 .

Here, the transmission efficiency is R as a parameter of the convolutional code.
When one constraint length is K, these are defined as follows.

Transmission efficiency R = B/Nt (B: number of inputs of f-'1 encoder, Nt: number of encoded outputs) Constraint length K (K: number of shift register stages of encoder) 1st
In the example shown in the figure, the X convolutional code XI of the encoder shown in the 11th screen is connected from the wiring from the register 101 to the exclusive OR circuits 102 and 103, where R2 172 and K=3. Generation function Gl for X2.

G2 is as follows.

Gl=1+D+D" G2=1 +D Also, the state in the convolutional encoder can be expressed by the states of the first stage a and the second stage in the register 101 shown in FIG.

In the case of a three-stage shift register, the data in the final stage is output to the outside every time an input is received, so the state transition is determined by the data in the first stage a and the next stage 1]. Generally, the number of states Ns of the convolution code is N5=2B·(K-1), where B indicates the number of manpower for the convolution code as described above.

Therefore, in this example, Ns=2.

In the case of 23, the data for a and b is ro,
0Jr1. ．． Four states are possible: 0JrO, IJrl, and lj. This state changes as shown in FIG. 2 every time a new input is received.

In Fig. 2, the solid arrow indicates that the input signal is I=00.
Shows the state transition at the time. The arrow shown by the dotted line indicates the state transition when the human input signal ■ is I-1. The logic codes 0 and 1 attached to each arrow indicate two exclusive OR circuits 102 and 10.
The convolutional codes Xi and X2 output from 3 are shown.

\minimum inter-symbol distance of convolutional code]') mjn is determined by the generation functions G1 and 02 of the encoder. This minimum inter-symbol distance Dmin is K (the number of stages of the shift register 101), the larger the dog is.3, Error correction of Viterbi decoding method 11-
Issue 1; t increases as Dsmn increases. In the example of Figure 2, t: 4 minimum? The Q monthly distance D-rn is D-open=5.

(2) Regarding the Viterbi decoding circuit, FIG. 3 shows the configuration of a conventional Viterbi decoding circuit.

The Viterbi decoding circuit can be mainly configured by an AC8 circuit group 302 and a path memory section 303. If the output side performs parallel serial conversion and converts /ζ\ convolutional codes X1 and X2 into serial codes and sends them out, AC8 circuit group 3
A serial-to-parallel converter 301 is required before 02. , in order to faithfully execute the Ushita Viterbi decoding method, the path memory unit 30 is required.
The 3° AC8 circuit group 302, in which the maximum likelihood determination unit 304 is provided at the subsequent stage of the 3° AC8 circuit group 302, is specifically constructed as shown in FIG. 401a, 401b, 40 in FIG.
1c, 4. Each Qld represents one Acs circuit.

Since each AC8 circuit has the same structure, each internal part will be explained using the same reference numerals.
, 403, 404, and 405 are logical adders, 406 is a comparator, 407 is a likelihood selector, and 408 is a bus selector.

Further, 409 indicates a likelihood register that takes in the likelihood output from the likelihood selector 407 and temporarily stores it.

The number of parallel output bits of this likelihood register 409 is selected to be more than twice the number of input bits to the AC8 circuit. The reliability of the obtained likelihood is improved by increasing the number of parallel outputs.

In the example of FIG. 4, A, /
D A converter 411 is provided, and this A/D converter 411 converts the serial convolution codes into levels 1 to 1.
A case is shown in which a soft decision is made as to whether the value is "1" or rOJ, and the error correction gain of the Viterbi decoding circuit is improved by this soft decision.

For example, if the number of quantization bits of the A/D converter 411 is 3
In terms of bits, the received codes input to each logic adder 402 and 403 are 3 bits each, making a total of 6 bits input. Therefore, the logic adder 402,4 (1:3
il, each consisting of three 3-bit full adder circuits. Also, the likelihood register 409 is 6 because 3X2=6.
Selected for registers with parallel output bits greater than 0.

(3) FIG. 5 shows the specific configuration of the path memory section 303.

501a, 501b, 501c, 501d shown in FIG.
indicates the wooden sword terminal of the path select signal. These path select signal input terminals 501a, 501b+501c, 501
Path selection signal signals 502a, 502 supplied to d
b, 502c, and 502d are registers 50 with selection functions.
3 selection terminals. First stage register 503a
, 503b, 503C, and 503d are commonly connected, and 503a and 503c have "0" at the common connection point.
” logic, and 503b and 503dK provide “1” logic.

The connection of each register 503 after the second stage corresponds to the state transition diagram shown in FIG. Captures the signal being supplied to the terminal. If the path select signal is ``1'' logic, the signal supplied to the lower input terminal shall be taken in. 3゜(4) Viterbi decoding procedure (when 1 = 1) (b) The after-tone signal is subjected to a Q-bit soft decision by the A/'D converter 411 (the larger Q is, the larger the coding gain can be obtained)/the partial sequence convolution including disturbance is eliminated in the rebalance converter 301. ＞=Y l , converted to Y 2.

(o) The likelihood (metric) for each state of the received signal is calculated in the logical adders 4-02 and 403, and branch metrics B and B' are determined.

(・→ The branch metrics B and B1 output from the logical FJn calculator 402 and 4.03, and the likelihood register 4
The current path metric candidate (2X in R-1
Ns pieces) are calculated.

(d) In each state, the comparator 406 (c) compares the path metric links output from the logical adders 404 and 405, takes in the likelihood (met link) of the path with the larger path metric into the likelihood selector 407, and Select signal - 'i' Selected by C path selector 408. As a result, Ns metrics and paths survive.

(E) The path selector 408 selects the selected Sareta Hass Select Den-"rJ is supplied to the path memory section 303, selects a path sequence according to the path select signal, and selects the path sequence from the path memory section 30.
Update the contents of the registers that make up 3.

(f) The maximum likelihood determining unit 304 compares the metrics of each state 12 and outputs the information of the final stage of the path memory register of the state having the maximum likelihood metric link as a decoded output.

(a) By repeating the operations in (g), a state having the most likely metric and its path sequence are always obtained, and a positive data sequence is estimated.

<Disadvantages of the Prior Art> In the above explanation, the case where the Tabi decoder circuit is set to 3 in the Viterbi encoder has been explained. K-: If it is 3, it is A.
The C8 circuit group 302 includes four sets of AC8 as shown in FIG.
It is sufficient to prepare the circuits 401a to 401d.

However, =3 is insufficient to make the error correction gain practical. In practice, it may be necessary to select around 1-7. When K = 7, N s =
64, and the AC8 circuit requires 64 silks. Therefore A
The circuit scale of the C808 circuit 02 is 3°.Furthermore, the number of soft decision bits of the received signal (corresponding to the number of A/D conversion bits) is Ql.If the number of metric bits is M, for example, in the case of R-1, each status AC8 circuit (401a, 401
The inputs to Q'-1 bit branch metrics, M-bit metrics from the two states making a transition to that state, and a 1-bit path select signal (of the probability of transition) are input to outputs a signal indicating which of two states has been selected as the survivor.

In this case, the calculation accuracy of the AC8 circuit increases as M increases, and the surviving path sequence and its metric values also become more accurate, but increasing M increases the circuit scale.

At this point, the Viterbi decoding circuit actually made is K =
The limit is about 5. If Tsuruni = 5, N5 = 16
Therefore, only 16 AC8 circuits are required. In order to realize 16 AC8 circuits, the number of OK gates is required, and this number of gates is the limit with current LSI technology. Therefore, according to the actual LSI technology, the limit is approximately 5, which is insufficient for practical use, although it is small.

<Objective of the Invention> The present invention aims to provide a Viterbi decoding circuit which simplifies the AC8 circuit and is sufficiently practical even with actual LSI technology.

<Summary of the Invention> In this invention, each arithmetic operation in the AC8 circuit is made into a table, this table is stored in a memory such as a ROM, and the reception signal and the likelihood of the previous bit are read out from this memory as an address signal. It is configured to obtain a predetermined path select signal and a new likelihood.

Therefore, according to the present invention, the AC808 circuit 02 can be replaced with a ROM, and a Viterbi decoding circuit with a large decoding gain can be easily realized.

<Embodiment of the Invention> FIG. 6 shows an embodiment of the invention. In FIG. 6, parts corresponding to those in FIGS. 3 and 4 are indicated by the same reference numerals.

In this invention, the Acs circuits 401a, 40
lb, 401C, ---40In is constituted by a memory such as a ROM, the received signal and the likelihood of one bit before are supplied to this memory as an address signal, and the table stored in the memory is read from this address signal. The path selection signal and the new likelihood are drawn.

An example of a table stored in memory is shown below.

In this example, a table corresponding to the AC8 circuit 401a shown in FIG. 4 is illustrated. This AC8 circuit 401a is an A, CS circuit that calculates the likelihood of states ro and OJ in the state transition diagram shown in FIG.

In the example shown below, a case is shown in which the transmission efficiency is R-1 and the constraint length is set to =3.

- Also, let the received signal be 1 bit each of XI and X2, and the path node link in state (0, O) is P (P is Ml).

M2. (represented by 3 bits of M8).

The path metric of state (0, 1) is p'(p' is Ml"
, M2', M3').

The overflow signal that detects just before the overflow of likelihood register 4.09 and normalizes the contents of the likelihood register is O.
In order to explain the process of calculation in the conventional AC8 circuit, the branch metrics to be output from the logic adders 402 and 4.03 are shown as B and B'.

The new path metrics to be output from the logical adders 406 and 407 are Pn and Pn'.

If the path select signal to be output from the path selector 4.08 is Pso, then the memory address signals (dx+, X2, P(Ml
, M2, Ms), P'(M1', M2', M3'),
Becomes an OF. The readout output of the trench table is Ml, M2.
M8, ps.

Table ■ The principle of manufacturing this table ■ will be explained below in conjunction with the specific circuit shown in FIG.

Received signal XI, Xi! is “1,1”, so the branch metric B is B = “0.
As is clear from the transition diagram, there is no possibility that the received signals X1, Therefore, the logical adder 40
The branch metric B to be output from 2 is B20.

In the state of ``ro, 1'', the received signal XI
, X2 is rl, t'', the state transitions to r O, OJ. Therefore, the branch metric B' to be output from the logic adder 403 is B'=2 (assumed to be the same as the number of bits in which the received signal matches the conditions necessary for transition).

As a result, the logical adders 404 and 405 calculate the current likelihood 1'i
f P and the likelihoods P'KB and B'' of the AC8 circuit 401C that calculates the likelihood of the state of "0, 1" are added, and a new likelihood P
Find n and pn''. Here, P (Ml , M2゜M8
) is r 0 , 1 , ], as shown in the daple ■.
J, which represents the number 3. Also P' (Ml”
, M2°, Mao) is IQ, 1. Since it is OJ, the number is 2.
represents.

Therefore, P n = P + B = O + 3 = , 3Pn
'=P'+B=2-1-2=4.

The comparator 406 compares Pn and Pnl and calculates Pn(Pn'
Determine. Based on this determination result, Pn'=4 is selected, inputted into the likelihood register 409, and Pnl is output. Therefore, the outputs Ml, M2. M and l become "], 0.0" and a likelihood of 4 is output. In the case of a trench, if Pn (pn') is selected and the likelihood rWpl of another system is selected, the path metric Ps is assumed to output Ps=1.

In this example, since the overflow normalized signal OF Lj is 0, the likelihood in the likelihood register 409 is output as is without being normalized.

Since the AC8 circuit drawn by the conventional arithmetic circuit performs arithmetic operations in this way, input signals are used as address signals XI, X2, Ml, M2, M8, Ml'
, M2', M8'OF, and this address signal is r 1, 1, 0, 1, 1, 0, 1, 0 as shown in the table.
．． When input as OJ, r ], , from memory
The table may be stored in memory so that "0, 0.1" are output.

Table (2) Principle of creation of daple C) In this case, the branch metrics B and B1 are B-1,1
3'=]. In this case, XI and X2 are r
Since O, 1, J, r> transitions to the state IO, Oj.
The degree of agreement is half that of the J function's Shin-Yumi IO, OJkarl, and IJ. Therefore, branch metric I321,
B'=1.

The addition of the logic adders 404 and 405 is as follows: P n = P 4- B = 2 + 1 = 3P
n'-=P'+B'=1+]=2 The magnitude relationship between Pn and Pnl is Pn)Pn'. Therefore, the likelihood Pn is output to the likelihood register 409, and this likelihood Pn is output.

Here, since the overflow normalized signal OF is "O", this likelihood Pn is output as is. Therefore, the outputs 1 to 1, M2. M8 is r 0 , 1 ,
1 j, and output a mark corresponding to P n = 3. ′! , the path select signal Ps is Pnl in this one column.
Since we have selected the likelihood P of the switching self, let J)s be 20.

Preparation principle of table ■ Receiving column ' X l , X 2 is r o , o-1
Therefore, the branch metric B and B1 digits B2. B
'=0.

P n = P - + - B = 4 + 2 = 6P
n'=P'-t-B'=0+0=Opn)pn' Now p n = 5, and the likelihood register 409 is in the state immediately before overflow. Therefore, the overflow normalization signal OF becomes 11'' and the likelihood is normalized. This normalization is performed by subtracting, for example, 2 from the data values of all likelihood registers 407. The likelihood output as a result is pn
=4, and one output Ml.

M2. Mll is set to rl, O, and OJ corresponding to 4.

In this case, the path metric Ps is also pn) pn'
Since the self likelihood P is selected, P s = O.

<Effects of the Invention> In this way, the calculation results in each AC8 circuit 401a to 401d can be tabulated, so even if the constraint length K is large, replacing it with memory such as ROM can save more time than when using an AC8 circuit. The circuit scale can be significantly reduced. Therefore, for example, the constraint length K = 7 and 1~, N5-6
4 can be realized by using 64 ROMs with a relatively small capacity of 5j. With this N, as is clear from the structure of the conventional AC8 circuit shown in Figure 4, the feedback loop becomes 401.
Since it is shared by AC8 circuits 401a and 401b and 401c and 401d, the amount of wiring can be reduced by storing the tables corresponding to these AC8 circuits 401a and 401b and 401C and 401d in a common ROM. can. Therefore, if two tables are configured to store one ROMK, even in the case of a circuit with N5 = 64, 32 R
This means that it can be configured with OM. Therefore, a sufficiently accurate Viterbi decoding circuit can be created using actual LSI technology.

Note that the maximum likelihood determination unit 304 can also be replaced with a ROM. However, when selecting the constraint length K to a value of 7 or more, the output of each final stage of the path memory section 303 has high reliability. Therefore, the maximum likelihood determination section 304 is not necessarily required. Instead of 304, a majority vote may be taken for each output of the HIS 303, and the output may be determined by the majority vote.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining the convolutional encoder, Figure 2-1 is a flowchart for explaining the state transitions of the convolutional code, and Figure 3 is the entire circuit for conventional Viterbi decoding. Figure 5 is a block diagram for explaining one configuration, Figure 5 is a connection diagram for explaining a conventional AC8 circuit, and Figure 5 is a diagram for explaining the specific structure of the path memory section used in the Hiribi decoding circuit. FIG. 6 is a block diagram for explaining one embodiment of the present invention. 302: A CS Ir! l path group, 3o3: path memory section, :u04: maximum likelihood determination section. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] (1) At least an AC8 circuit that calculates the likelihood corresponding to each state representing a combination of information bits included within the constraint length of the ζN convolutional encoder, and a path select signal obtained from this AC8 circuit is stored. In a Viterbi decoding circuit comprising a path memory circuit, the AC8 circuit is configured by a memory that stores the results of the above calculation in the original AC8 circuit as a table, and the received convolutional code and the previous bit are stored in this memory. A Viterbi decoding circuit characterized in that the likelihood of a predetermined path select signal and a new likelihood are obtained by supplying the likelihood of the address signal as an address signal and reading the table.