JP2004193892A - Viterbi decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Viterbi decoder capable of decoding based upon the maximum likelihood path even when there is states having the same path metric among a plurality of states at a specified point of time of a trellis diagram or when there are many states having similar path metrics. <P>SOLUTION: The Viterbi decoder is equipped with an ACS circuit 22 which finds path metrics of a plurality of paths on the trellis diagram as to a signal which lasts by a trace-back length shorter than a data bit length after decoding among encoded signals transmitted after convolutional encoding and a MAX path metric reliability decision unit 225 which selects one of the plurality of paths according to the path metrics or selects one path according to last path metrics if one of the paths cannot be selected according to the path metrics. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a Viterbi decoder for decoding a coded signal transmitted by convolutional coding in units of a traceback length shorter than the data bit length of a decoded word.
[0002]
[Prior art]
When transmitting information represented by a digital signal, it is expected that accurate information will not be transmitted due to the influence of noise or the like during transmission. Conventionally, in order to transmit information accurately even if it is affected by noise during transmission, the digital signal representing the information is converted into a code word using various algorithms to provide redundancy. It has been practiced to generate an encoded signal and transmit the encoded signal. Also, by decoding the transmitted coded signal on the receiving side, accurate information can be obtained even if a part of the coded signal has been changed due to the influence of noise or the like.
[0003]
As an example of an encoder that generates a codeword on the transmission side, there is a convolutional encoder, and as a decoder for decoding an encoded signal transmitted by being convolutionally encoded by the convolutional encoder on the reception side, Conventionally, a Viterbi decoder has been used.
[0004]
FIG. 1 is a diagram schematically illustrating the relationship between a convolutional encoder and a Viterbi decoder.
[0005]
An information signal sequence a ₁ a ₂ a ₃ ... In which information to be transmitted is represented by a series of 1-bit information signals is input to the convolutional encoder 100 shown in FIG.
[0006]
The information signal sequence a ₁ a ₂ a ₃ ... Inputted to the convolutional encoder 100 is converted into a code word composed of a predetermined number of bits for each bit, and a coded signal which is a sequence of this code word is converted to a convolutional encoder. It is output from 100. This encoded signal is input to the Viterbi decoder 200 via the transmission path. The Viterbi decoder 200 decodes a coded signal that may be affected by noise on the transmission path, and has a decoded signal sequence a ₁ having the same content as the information signal sequence before being coded by the convolutional coder 100. a ₂ a 3 _... to output.
[0007]
Here, when decoding the encoded signal, a decoding process called a Viterbi algorithm using a trellis diagram (described later with reference to FIG. 3) corresponding to the convolutional encoder 100 that generated the encoded signal is performed by a digital circuit. Is a Viterbi decoder 200.
[0008]
In the above trellis diagram, all the encoded signals that the convolutional encoder 100 will generate based on the information signal of a predetermined data bit length are obtained and shown based on the circuit configuration of the convolutional encoder 100. ing. From the coded signals shown in the trellis diagram, a coded signal having a data structure closest to the coded signal received by the Viterbi decoder 200 is selected, and a code is selected from the selected coded signal. The decoding process of estimating the information signal before being converted is the Viterbi algorithm.
[0009]
As described above, the encoded signal received by the Viterbi decoder 200 may be partially changed due to the influence of noise or the like. On the other hand, the encoded signal shown in the trellis diagram is accurate because it is theoretically obtained from the convolutional encoder. In the Viterbi algorithm, since an information signal is estimated based on an accurate coded signal shown in a trellis diagram, it is possible to perform accurate decoding in which influences such as noise during transmission are eliminated.
[0010]
Here, before describing the Viterbi decoder, a convolutional encoder will be described first.
[0011]
FIG. 2 is a block diagram illustrating an example of the convolutional encoder.
[0012]
The convolutional encoder 110 shown in FIG. 2 includes two shift registers 111 and 112 connected in series to each other, and five arithmetic units 113, 114, 115, 116 and 117 for performing exclusive OR. It is configured.
[0013]
In Figure 2, already the first information signal _{a 1} and the second information signal _{a 2} to the shift register 111 and 112 of the convolutional encoder 110 is stored, the time when the third information signal _{a 3} is input 2 shows the convolutional encoder 110 in the state at the second time point where the 3-bit code word G ₁ G ₂ G ₃ has been output.
[0014]
The state of the convolutional encoder 110 shown in FIG. 2 is a ₂ a ₁ . As this convolution in the shift register 111 of the encoder 110 is the information signal a ₃ is stored, the information signal a ₂ of the first-stage shift register 111 is stored in the shift register 112 of the second stage. Thereafter, a new 3-bit codeword is generated and output based on a new information signal (not shown) and two information signals a ₂ a ₃ that are input. In other words, the storage in the shift register 111 of the convolutional encoder 110 of the information signal _{a 3,} the state of the convolutional encoder 110 _transitions from a 2 _{a 1} to _a 3 _{a 2.}
[0015]
As described above, in the convolutional encoder 110 shown in FIG. 2, one 3-bit codeword is generated every time one bit of an information signal is input, and the state of the codeword changes.
[0016]
Next, a trellis diagram will be described.
[0017]
FIG. 3 is a trellis diagram in the convolutional encoder shown in FIG.
[0018]
The trellis diagram shown in FIG. 3 shows all codewords generated by convolutional encoder 110 (see FIG. 2) based on an information signal sequence having a data bit length of 7 bits and state transitions at that time. The state of the convolutional encoder 110 is represented by a combination of two bits. Therefore, the convolutional encoder 110 has four states 00, 10, 01, and 11. In the example of FIG. 3, the initial state of the convolutional encoder 110 when it is in the initial state at time 0 is set to 00.
[0019]
In the example of FIG. 3, the data bit length of the information signal sequence input to convolutional encoder 110 is 7 bits. Therefore, the last information signal of this information signal sequence is input, and the convolutional encoder 110 completes generation of the last codeword based on this information signal at the seventh time. In the example of FIG. 3, the last two bits of the information signal sequence are set to 00 so that when the convolutional encoder 110 completes the generation of the encoded signal, the state becomes 00 which is the same as the initial state. I have. Therefore, the state of the convolutional encoder 110 at the seventh time point is 00.
[0020]
In the trellis diagram shown in FIG. 3, the state at each time point is represented by a black circle, and the transition from the state at a certain time point to the state at the next time point is represented by an arrow. In the vicinity of each arrow, a code word corresponding to the state transition indicated by the arrow is added.
[0021]
Here, each arrow is referred to as a branch, and a transition from a state at a certain point in time to a state at another point one or more points away from the state at one or more points is referred to as a path. For example, a transition from state 00 at time 0 to state 10 at time ₁ is represented by branch b1. The transition from the state 00 at the time point 0 to the state 11 at the time point ₂ is represented by a path P that combines _two branches b ₁ and b ₂ . The codeword added to each branch is estimated from the circuit configuration of the convolutional encoder 110, and is referred to herein as an estimated codeword.
[0022]
Further, for convenience of description, in the trellis diagram, a branch heading toward a state at a certain time is referred to as a branch at that time. For example, in the trellis diagram shown in FIG. 3, a branch b ₃ coming towards one point th state 00, the branch b ₁ coming towards the state 10 one time th is a one time th branch .
[0023]
A decoding process for decoding an encoded signal using such a trellis diagram is a Viterbi algorithm, and a Viterbi decoder realizes decoding using the Viterbi algorithm with a digital circuit.
[0024]
Here, a Viterbi decoder that performs decoding based on the Viterbi algorithm on a coded signal transmitted after being subjected to convolutional coding in units of a traceback (to be described later with reference to FIG. 4) shorter than the data bit length after decoding. Has been proposed (for example, see Patent Document 1).
[0025]
[Patent Document 1]
JP-A-11-355150 (paragraph number 0011-0071, FIG. 6, FIG. 11)
[0026]
[Problems to be solved by the invention]
FIG. 4 is a block diagram showing a Viterbi decoder disclosed in Patent Document 1.
[0027]
Here, in describing the Viterbi decoder 210 shown in FIG. 4, the encoder that generates the encoded signal is the convolutional encoder 110 shown in FIG. 2, which is realized by the Viterbi decoder 210. It is assumed that the decoding process uses the trellis diagram shown in FIG. 3 corresponding to the convolutional encoder 110. This is the same in the description of FIG. 5 described later.
[0028]
The encoded signal transmitted to the Viterbi decoder 210 shown in FIG. 4 is a sequence of codewords generated by the convolutional encoder 110 in the order of generation. This encoded signal is input to the branch metric calculator 211 of the Viterbi decoder 210. In the branch metric calculation process executed by the branch metric calculator 211, each time one code word constituting the coded signal is input, the time when this code word is generated and the time when the code word is generated are shown in FIG. A branch metric is calculated for the branch that coincides in time. Here, the branch metric is the number of digits for which the value of the corresponding digit does not match when the estimated codeword added to the branch is compared with the codeword input to the Viterbi decoder 210 for each digit. . For example, it is assumed that the codeword generated at the first time is 001. At the first point in the trellis diagram, there are two branches b ₁ and b ₃ . Estimated code word is appended to the branch b ₁ is 111. When the estimated code word 111 and a code word 001 compares each digit, because the number of those values of the corresponding digits do not match is two, branch metrics of the branches b ₁ is two. Also when similarly calculated branch metric of the branch b ₃ becomes 1. Information indicating the branch metric obtained by the branch metric calculator 211 is supplied to an ACS (Add Compare Select) circuit 212.
[0029]
The ACS circuit 212 executes the following ACS process based on the information indicating the branch metric supplied from the branch metric calculator 211.
[0030]
First, the path metric of the state is calculated. Here, the path metric of the state is obtained by calculating the cumulative value of the branch metric of the branch constituting the path for a path to a certain state on the trellis diagram (see FIG. 3). In the ACS process, when information indicating a branch metric of a branch connected to a certain state is supplied from the branch metric calculator 211, on the trellis diagram, information indicating a path metric of a state connected by this branch one time before is determined. It is read from the path metric memory 213. The path metric is calculated by adding the branch metric indicated by the information supplied from the branch metric calculator 211 to the path metric of the state immediately before the time indicated by the information. Information indicating the calculated path metric is stored in the path metric memory 213 and used for calculating the path metric at the next point in time.
[0031]
Here, for example, in the 3 point-th state 00 of the trellis diagram, a branch b ₄ from 2 time th state 00, the two branches of a branch b ₅ from the state 01 of the two points in time th led ing. This is because there are two types of paths from state 00 at time 0 to state 00 at time 3, a path passing through state 00 at time 2 and a path passing through state 01 at time 2. Means to exist. As described above, when there are two types of paths to a certain state, the ACS process calculates path metrics for the two types of paths, and selects a path having a smaller value as a path to this state. Here, the selected path is referred to as a surviving path. Information indicating the surviving path is stored in the surviving path memory 214. Information indicating the path metric of the surviving path is stored in the path metric memory 213.
[0032]
In the ACS process, the calculation of the path metric and the selection of the path are performed for all the states at each point in the trellis diagram.
[0033]
When the ACS process executed in the ACS circuit 212 is executed up to a predetermined point in the trellis diagram, the MAX path metric determiner 215 determines one state having the smallest path metric from among the states at that point in time. A selection process of selecting one is performed. Information indicating the state obtained by this selection process is supplied to the traceback circuit 216.
[0034]
The traceback circuit 216 that has received the information indicating the state from the MAX path metric determiner 215 reads the information indicating the path leading to this state from the surviving path memory 214.
[0035]
Here, according to the path indicated by this information, an estimated codeword string in which the estimated codewords added to the branches making up this path are listed in the trellis diagram from time 0 to the above-mentioned predetermined time Is an estimated code word sequence having a data structure closest to the encoded signal transmitted to the Viterbi decoder 210 among the estimated code word sequences similarly created for all the paths shown in FIG. . Here, the path corresponding to the estimated code word sequence is referred to as the maximum likelihood path.
[0036]
The traceback circuit 216 executes a process of estimating the information signal sequence input to the convolutional encoder 110 based on the maximum likelihood path, and outputs the estimated result as a decoded signal sequence. Estimating the time order from the information signal a ₁ which is immediately before the first time point th, the selection of the state is performed until a predetermined time which is performed by the MAX path metric determiner 215. This estimation process is called traceback, and the data bit length of the decoded signal sequence obtained by one traceback is called traceback length.
[0037]
The operation of each unit of the Viterbi decoder 210 is controlled by the control circuit 217.
[0038]
Here, in the decoding based on the original Viterbi algorithm, the calculation of the path metric and the selection of the path in the ACS process are repeated until the last time point of the trellis diagram (see FIG. 3), so that the state 00 at the 0 time point to the last One of the maximum likelihood paths leading to state 00 is determined. However, if decoding by the original Viterbi algorithm is to be realized by a digital circuit, a large-scale path metric memory 213 and a surviving path memory 214 for storing information such as path metrics and surviving paths obtained during decoding are used. A simple memory circuit is required. Therefore, in the Viterbi decoder 210 shown in FIG. 4, the ACS process in the ACS circuit 212 is interrupted once at a predetermined time by the MAX path metric determiner 215, and the traceback shorter than the data bit length after decoding is performed. By performing decoding in units of length, the circuit scale of the path metric memory 213 and the surviving path memory 214 is suppressed.
[0039]
In the Viterbi decoder 210 shown in FIG. 4, when the traceback ends, the ACS process is restarted. Here, the initial state at the time of resumption is a state obtained by the selection process executed by the MAX path metric determiner 215 before traceback. In this way, the Viterbi decoder 210 repeats decoding in units of traceback length, and decodes all information signal sequences.
[0040]
As described above, the Viterbi decoder 210 shown in FIG. 4 determines the smallest path metric from the plurality of states at a predetermined time by the selection process executed by the MAX path metric determiner 215. One state is selected, and a path leading to this state is set as the maximum likelihood path, and traceback is executed based on the maximum likelihood path.
[0041]
However, in the Viterbi decoder 210 shown in FIG. 4, when a plurality of states having the same path metric or a plurality of states having a similar path metric exist among the plurality of states at the predetermined time, There is a risk that a wrong path is selected and wrong decoding is performed based on this path.
[0042]
The present invention has been made in view of the above circumstances, even when a plurality of states having the same path metric or a plurality of states having a similar path metric exist among a plurality of states at a predetermined time in a trellis diagram, It is an object of the present invention to provide a Viterbi decoder that can execute decoding based on the maximum likelihood path.
[0043]
[Means for Solving the Problems]
The Viterbi decoder of the present invention, which achieves the above object, comprises a plurality of convolutionally-encoded coded signals having a traceback length shorter than the data bit length after decoding, which is continuous on a trellis diagram. A path metric calculation unit that obtains a path metric of the path, and one of the plurality of paths is selected based on the path metric calculated by the path metric calculation unit. A path selecting unit that selects any one path based on the immediately preceding path metric obtained by removing the immediately preceding branch metric from the path metric when it is impossible to select one of the paths. Features.
[0044]
A Viterbi decoder according to the present invention is a path selection unit that selects any one path from a plurality of paths on a trellis diagram, based on the immediately preceding path metric obtained by removing the immediately preceding branch metric from the path metric of the path. It has. Therefore, for example, there are a large number of paths having the same path metric or paths having similar path metrics. Based on these path metrics, the maximum likelihood path is determined as one of the paths on the trellis diagram. Even when it is not possible to select one, the path with the highest likelihood can be selected by the above-described path selection unit.
[0045]
Here, in the Viterbi decoder according to the present invention, the path selection unit determines whether the reliability of the immediately preceding branch metric is high or low, and when the reliability is low, any one of the branch metrics based on the immediately preceding path metric. It is preferable to select a path.
[0046]
In such a Viterbi decoder, only when the reliability of the immediately preceding branch metric is low, a path is selected based on the immediately preceding path metric, so that the efficiency of the decoding process is improved.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0048]
FIG. 5 is a diagram showing one embodiment of the Viterbi decoder of the present invention.
[0049]
The Viterbi decoder 220 shown in FIG. 5 includes a branch metric calculator 221 for executing a branch metric calculation process, an ACS circuit 222 for executing an ACS process, a path metric memory 223 for storing information indicating a path metric, and a surviving path. A survivor path memory 224 for storing information indicating a state, a MAX path metric reliability determiner 225 for executing a selection process of selecting any one of a plurality of states at a predetermined time in a trellis diagram, and a traceback. It comprises a traceback circuit 226 to be executed and a control circuit 227 for controlling the operation of each part of the Viterbi decoder 220.
[0050]
Here, the configuration and operation of the Viterbi decoder 220 shown in FIG. 5 are the same as the configuration and operation of the Viterbi decoder 210 shown in FIG. 4 except for the MAX path metric reliability determiner 225. Therefore, the description of the same points as those of the Viterbi decoder 210 shown in FIG. 4 will be omitted here, and only the difference, that is, the MAX path metric reliability determiner 225 will be described.
[0051]
When the ACS process in the ACS circuit 222 ends up to a predetermined time corresponding to the traceback length on the trellis diagram, the MAX path metric reliability determiner 225 performs the following procedure from a plurality of states at that time. , A selection process for selecting one of the states is performed.
[0052]
First, a state having a minimum path metric is selected from a plurality of states.
[0053]
Next, an upper limit value is calculated by adding a predetermined numerical value to the minimum path metric. Further, a state having a path metric falling within the range from the minimum path metric to the above upper limit is selected from a plurality of states.
[0054]
If the number of selected states is one, information indicating this state is output to the traceback circuit 226.
[0055]
If there are a plurality of selected states, the branch metrics of the branches connected to these states are read from the branch metric calculator 221 to determine the reliability of these branch metrics. If it is determined that the reliability is high, the state having the minimum path metric is selected from the plurality of selected states. If there are a plurality of states having the minimum path metric, one state is selected from the plurality of states having the same path metric according to a predetermined rule, and information indicating this state is selected. Is supplied to the trace-back circuit 226.
[0056]
When the reliability of the branch metric is determined to be low as a result, first, for each of the selected states, 1 is obtained by removing the immediately preceding branch metric from the path metrics of these states. The path metric before the time point is read from the path metric memory 223. Next, from among the plurality of selected states, one state in which the path metric one time earlier is minimized is selected. Information indicating one selected state is output to the traceback circuit 226.
[0057]
As described above, the MAX path metric reliability determiner 225 determines that a plurality of states having the same path metric or a plurality of states having a similar path metric exist among a plurality of states at a predetermined point in the trellis diagram. In such a case, one state can be selected.
[0058]
Since the Viterbi decoder 220 of the present embodiment performs a traceback based on the maximum likelihood path leading to the state selected in this way and outputs a decoded signal sequence, it is possible to improve the decoding gain. Become.
[0059]
【The invention's effect】
As described above, according to the Viterbi decoder of the present invention, among a plurality of states at a predetermined time in a trellis diagram, there are many states having the same path metric or a number of states having similar path metrics. In such a case, decoding based on the maximum likelihood path can be performed. Therefore, the decoding gain can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating a relationship between a convolutional encoder and a Viterbi decoder.
FIG. 2 is a block diagram illustrating an example of a convolutional encoder.
FIG. 3 is a trellis diagram corresponding to a convolutional encoder.
FIG. 4 is a block diagram showing a conventional Viterbi decoder.
FIG. 5 is a diagram showing one embodiment of a Viterbi decoder of the present invention.
[Explanation of symbols]
100, 110 Convolutional encoders 111, 112 Shift registers 113, 114, 115, 116, 117 Operators 200, 210, 220 Viterbi encoders 211, 221 Branch metric calculators 212, 222 ACS circuits 213, 223 Path metric memory 214, 224 Surviving path memory 215 MAX path metric decision unit 216, 226 Traceback circuit 217, 227 Control circuit 225 MAX path metric reliability decision unit

Claims (2)

In a Viterbi decoder that decodes a coded signal transmitted by convolutional coding in units of a traceback length shorter than the data bit length after decoding,
A path metric calculation unit that obtains path metrics of a plurality of paths on a trellis diagram of the signal having the traceback length continuous among the encoded signals,
It is not possible to select any one of the plurality of paths based on the path metric calculated by the path metric calculation unit and to select any one of the paths based on the path metric. A path selection unit that selects any one path based on the immediately preceding path metric obtained by removing the immediately preceding branch metric from the path metric. The path selection unit may determine whether the reliability of the immediately preceding branch metric is high or low, and when the reliability is low, select one of the paths based on the immediately preceding path metric. The Viterbi decoder according to claim 1, wherein

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