JPS59152726A - Reset system in electronic circuit - Google Patents

Abstract

PURPOSE:To obtain a reset system with less malfunction at low impedance by controlling a bias value of a transistor (TR) by a contact of a relay operated at application of power supply and resetting the electronic circuit with an output of the said TR. CONSTITUTION:A contact sup of a relay SUP operated at application of power supply is connected in series to a resistor R0 as bias supply of the TR. When the relay SUP is operated, the TR is operated by a bias determined by resistors R0, R1 as a TR input current, an output point (p) of the TR goes to a high level to reset a flip-flop FF. Since the resistor R2 is set to a low resistance, a reset circuit resistant to external noise having a low impedance from both the power supply and earth is obtained by viewing it from the input side requiring resetting.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a reset method in an electronic circuit, and in particular, uses the timing of a relay operation to reset an electronic circuit.
Reception of information from the relay by a transistor relates to a reset method in which reset is performed by the output of the transistor.

11+1, Conventional Waves i, I・1 and Problems In the conventional Nyorori cent method, reset was performed using the timing determined by the charging and discharging time of the capacitor and resistor.

FIG. 1 shows an embodiment of a reset method according to the prior art, in which RO1R1 and R2 are resistors, C is a capacitor, G is a gate, and FF is a flip-flop.

If you want to create enough timing for a reset to occur using capacitor C and quick resistor RO, there are two ways to do this: use a large capacitor and small resistance, or use a small capacitor and large resistance. Frequency noise has the disadvantage that a short circuit occurs and a reset is applied incorrectly, and in the latter case, the resistance value is large, so the input of the element that requires reset becomes high impedance, so the noise jumps. There is a disadvantage that there is a high possibility that the reset will be reset by mistake.

(C)1 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
The purpose of the present invention is to provide a reset method for an electronic circuit that does not use a capacitor and is resistant to external noise and has stable operation without causing false resets.

(d) 3 Structure of the Invention According to the present invention, in an electronic circuit having elements that require initial setting, the emitter of a transistor f is grounded via a low resistance, and the collector of the transistor is directly connected to a power source. , by controlling the bias value of the transistor by a contact of a relay that operates when the power is turned on, a pulse voltage change occurring between the emitter of the transistor and ground is used as a reset signal, and the power supply is constantly monitored by the relay. This is achieved by providing a reset method in an electronic circuit characterized by the following.

(e) 1 Embodiment of the Invention The present invention utilizes the difference between the operating time of a relay and the operating time of an electronic circuit to provide more reliable cent timing, and further provides an external This is designed to eliminate erroneous cents caused by noise.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which Tr is a transistor, ROlRl and R2 are resistors, D is a diode, SUP is a relay, and FF is a flip-flop.

Note that the resistor RO has a low resistance, the resistor R1 has a high resistance, and the resistor R2 has a low resistance.

The present invention will be described in detail below with reference to FIG.

The contact sup of the relay SUP, which operates when the power is turned on, is connected to the resistor RO and the IK column as shown in FIG. 2 for supplying bias to the transistor Tr.

Therefore, when the relay SUP operates, the transistor Tr operates with the bias determined by the transistor input current and the resistor RO1R1, and the output p of the transistor Tr operates.
The point goes to a "high" level and resets flip-flop FF.

Resistor R2 can be set to a low resistance, so by using a circuit like this, from the perspective of the input side that requires reset, it has low impedance from both the power supply and ground, and is therefore resistant to external noise. It becomes a cent circuit.

(f) 1. Effects of the Invention As described in detail above, the present invention has the great effect of providing a low-impedance, malfunction-free reset method for a good electronic circuit.

[Brief explanation of drawings]

FIG. 1 shows an example of a reset method according to the prior art, in which ROSR1 and R2 are resistors, C is a capacitor, G is a gate, and FF is a flip-flop. FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which Tr is a transistor, ROSR1 and R2 are resistors, D is a diode, SUP is a relay, and FF is a flip-flop. Note that the resistor RO has a low resistance, the resistor R1 has a high resistance, and the resistor R2 has a low resistance. Leaves (Fig. 2)

Claims (1)

[Claims] In electronic circuits that include elements that require initial settings,
The emitter of the transistor is grounded via a low resistance, the collector of the transistor is directly connected to the power supply, and the bias value of the transistor is controlled by the contacts of a relay that operates when the power is turned on, thereby generating a pulse voltage change between the emitter of the transistor and the ground. 1. A reset method for an electronic circuit, characterized in that the power source is constantly monitored by the relay, and the relay is used as a reset signal.