JPS59152647A - Multilayer interconnection method - Google Patents

Multilayer interconnection method

Info

Publication number
JPS59152647A
JPS59152647A JP2829283A JP2829283A JPS59152647A JP S59152647 A JPS59152647 A JP S59152647A JP 2829283 A JP2829283 A JP 2829283A JP 2829283 A JP2829283 A JP 2829283A JP S59152647 A JPS59152647 A JP S59152647A
Authority
JP
Japan
Prior art keywords
air bridge
layer wirings
lower layer
film
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2829283A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2829283A priority Critical patent/JPS59152647A/en
Publication of JPS59152647A publication Critical patent/JPS59152647A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the yield of an air bridge by covering lower layer wirings with an insulating material which is softened at high temperature of 500 deg.C or lower, forming upper layer wirings, and removing by gas plasma the insulating material, thereby eliminating the restriction in the steps due to the stepwise disconnection and weakness in mechanical strength. CONSTITUTION:Upper layer wirings 22 cross lower layer wirings 21 through an insulating film 23 having a smooth section. The film 23 is etched by gas plasma which does not affect the influence to a substrate or wiring metal, thereby foring an air bridge in noncontact. After lower layer wiring metal 31 is formed by normal photolithographic and lift-off methods, a photoresist (OFPR-800) is formed on the entire substrate. A resist film 33 is allowed to remain only on the crossover of the upper and lower layer wirings forming the air bridge by the lithography and the peripheral regions, and baked at 200 deg.C for 20min. Then, upper layer wirings 32 are formed by the method equivalent to the lower layer wirings. The film 33 of air bridge structure is removed by plasma etching with oxygen gas an air bridge.

Description

【発明の詳細な説明】 技術分野 本発明は半導体基板上にトランジスタ、抵抗、コイル、
コンデンサ等の電子部品を形成し相互に接続したいわゆ
る集積回路の多層配線技術に関するものである。
[Detailed Description of the Invention] Technical Field The present invention provides transistors, resistors, coils, etc. on a semiconductor substrate.
This invention relates to multilayer wiring technology for so-called integrated circuits in which electronic components such as capacitors are formed and interconnected.

ここでは簡単のため本発明の効果が顕著に出現する場合
として半絶縁性カリウム砒素(以下GaAsと略す〕基
板上に形成された電界効果トラレジスタ(以下FETと
略す)を含む集積回路を例にとつて説明する。
For the sake of simplicity, we will use an example of an integrated circuit that includes a field-effect transistor (hereinafter referred to as FET) formed on a semi-insulating potassium arsenide (hereinafter referred to as GaAs) substrate as a case where the effects of the present invention will be noticeable. Let me explain.

背景技術 集積回路の動作速度を高速化し、かつ低消費電力化を図
るには素子の微細化回路の高集積度化が必須である。こ
れに伴ない各部品及びこれらを相互に接続するための配
線が近接し、さら゛に配線間の交叉部が増加することに
なる。
BACKGROUND ART In order to increase the operating speed of integrated circuits and reduce power consumption, it is essential to miniaturize elements and increase the degree of integration of circuits. As a result, each component and the wires for interconnecting these components are brought closer to each other, and the number of intersections between the wires further increases.

その結果、とくに配線容量が増加し、動作速度の低減に
つながる。これを防ぐために有効な配線間の・絶縁法が
必要となる。
As a result, the wiring capacitance in particular increases, leading to a reduction in operating speed. To prevent this, an effective insulation method between wires is required.

このような目的に対する有効な手段にエアブリッジ法が
ある。これは図1に示すように、集積回路内において、
下側の金属配線11と上側の金属配線12とが交叉する
場合に両者間に絶縁膜を介さず上側の配線金属が立体交
叉する多層配線技術である。この方法の特徴は2種の配
線は比誘電率の最も小さい空気で絶縁されているため他
の任意の絶縁膜を用いる場合に比して面配線間の容量が
最も小さくなることにある。このため回路内の配線容量
が低減され集積回路の動作速度が改善される。しかしな
がらこのエアブリッジは構造上上層配線が中空に浮いた
状態にあり、エアブリッジ形成後は表面に接触すること
かで・きなくなる。このため以後の工程において、以下
のような様々な技術的問題点・制約が生じる。
The air bridge method is an effective means for achieving this purpose. As shown in Figure 1, within the integrated circuit,
This is a multilayer wiring technology in which when the lower metal wiring 11 and the upper metal wiring 12 intersect, the upper wiring metal intersects three-dimensionally without interposing an insulating film between them. The feature of this method is that since the two types of wiring are insulated by air having the lowest dielectric constant, the capacitance between the plane wirings is the smallest compared to the case where any other insulating film is used. This reduces the wiring capacitance within the circuit and improves the operating speed of the integrated circuit. However, due to the structure of this air bridge, the upper layer wiring is suspended in the air, and after the air bridge is formed, it cannot come into contact with the surface. For this reason, various technical problems and restrictions such as those described below arise in subsequent steps.

すなわち、 ■)高周波特性向上のため基板厚さを裏面から薄くする
場合、化学エツチングに必!要な保護膜の形成が必要で
ある。一方、機械的研磨によって基板を薄くする場合、
基板表面に接触する必要がある。
In other words, ■) Chemical etching is essential when thinning the substrate from the back side to improve high frequency characteristics! It is necessary to form a protective film. On the other hand, when thinning the substrate by mechanical polishing,
Must be in contact with the substrate surface.

2)基板上に多数繰り返して形成された半導体装置を分
離し、チップ化するスフしイブ、七バレートの工程j4
−;J、、l!面に破片や汚れが付着したり傷を付けた
りすることを防ぐために裏面から加工処理を施すことが
多く、必然的に表面に接触することになる。
2) Separating semiconductor devices repeatedly formed on a substrate and making them into chips, a seven-part process j4
-;J,,l! In order to prevent debris and dirt from adhering to or scratching the surface, processing is often applied from the back side, which inevitably comes into contact with the front surface.

3)チップ化した半導体装置を一つずつパッケージへ装
着するボンディング工程ではコレットや真空ピンセット
にてチップ表面側を吸着することになる。
3) In the bonding process in which chipped semiconductor devices are attached to a package one by one, the surface side of the chip is attracted using a collet or vacuum tweezers.

4)最終的に集積回路に保護膜を形成する場合、外部へ
電気的接続をとり出すため保護膜に開口部を゛設ける。
4) When a protective film is finally formed on the integrated circuit, an opening is provided in the protective film in order to take out electrical connections to the outside.

ここで通常のコンタクト露光によるホトリソグラフィを
適用する場合、基板表面はホトマスクに強く密着される
ことになる。
If photolithography using normal contact exposure is applied here, the substrate surface will be tightly adhered to the photomask.

以上の工程または取扱いはエアブリッジを保護するとい
う点からは実施できないものであり、上述と同等の工程
を実施するためには煩雑な工程を附加することになる。
The above steps or handling cannot be carried out from the viewpoint of protecting the air bridge, and in order to carry out the same steps as those described above, complicated steps will be added.

この場合、半導体装置の生産性、歩留りが著しく悪化す
るという問題点が生じる。
In this case, a problem arises in that the productivity and yield of semiconductor devices are significantly deteriorated.

一方、エアブリッジ自身構造的に弱いものであり、僅か
の外力によっても上層配線が切れたり、下層配線と接触
することが多く歩留りが低いという問題がある。また、
配線間の接触を防ぐため上層配線をできるだけ高い位置
に形成することが多く段差切れの危険がある。
On the other hand, the air bridge itself is structurally weak, and there is a problem in that even a slight external force causes the upper layer wiring to break or come into contact with the lower layer wiring, resulting in a low yield. Also,
In order to prevent contact between wires, the upper layer wires are often formed as high as possible, and there is a risk of step breakage.

発明の開示 本発明は上記従来技術の問題点を解決する新しい多層配
線方法を提供するものである。
DISCLOSURE OF THE INVENTION The present invention provides a new multilayer wiring method that solves the problems of the prior art described above.

以下実施例に即して説明する。The following description will be made based on examples.

図2は本発明の実施例の一例を示すためのものであり、
滑らかな断面をもつ絶縁膜23を介して上層配線22が
下層配線21と交叉しているものである。絶縁膜23を
基板や配線金属に影響しないガスプラズマでエツチング
することにより非接触でエアブリッジが形成できる。以
下エアブリッジの製作たついての一例を、図8に示す工
程に沿って説明する。
FIG. 2 is for showing an example of an embodiment of the present invention,
The upper layer wiring 22 intersects with the lower layer wiring 21 via an insulating film 23 having a smooth cross section. By etching the insulating film 23 with gas plasma that does not affect the substrate or metal wiring, an air bridge can be formed without contact. An example of how an air bridge is manufactured will be described below along the steps shown in FIG.

通常のフォトリングラフィとリフトオフ法によって下層
の配線金属31を形成した後、基板全面に回転塗布法に
よりフォトレジスト(OFPR−800)を2.5μm
の厚さに形成する。リソグラフィに上ってエアブリッジ
を形成する上層・下層配線の交叉部とその周辺の領域に
のみレジスト膜33を残し、(E 3−(A)) 、2
00℃の温度で20分間ベークする。この時の温度はレ
ジストが軟化する温度より十分高温であるためレジスト
が流れ表面張力によって半球状の形状となる。図a −
(s)次いで下層配線と同等の方法により、上層配線8
2を形成する。
After forming the lower layer wiring metal 31 by ordinary photolithography and lift-off method, photoresist (OFPR-800) is applied to the entire surface of the substrate to a thickness of 2.5 μm by spin coating method.
Form to a thickness of . The resist film 33 is left only at the intersection of the upper layer and lower layer wiring and the surrounding area where the air bridge is formed by lithography, (E 3-(A)), 2
Bake for 20 minutes at a temperature of 00°C. The temperature at this time is sufficiently higher than the temperature at which the resist softens, so the resist flows and takes on a hemispherical shape due to surface tension. Figure a-
(s) Next, the upper layer wiring 8 is
form 2.

(図a −(C))絶縁膜38の断面は軟化して殆んど
円に近い状態であるため上層配線が絶縁膜の段差部で断
線するいわゆる段差切れが解消できる。
(Figures a-(C)) Since the cross section of the insulating film 38 is softened and almost circular, it is possible to eliminate so-called step breakage in which the upper layer wiring is broken at the step portion of the insulating film.

続いて酸素ガスによるブラズ゛掩エツチングによりエア
ブリッジ構造のフォトレジスト膜33を除去し、図8−
■)に示すようなエアブリッジとする。
Subsequently, the photoresist film 33 having the air bridge structure was removed by blast etching using oxygen gas, and the photoresist film 33 having the air bridge structure was removed.
■) Create an air bridge as shown in ().

以後、裏面研磨、スクライシ、セパレート、ボンディン
グ等の組立工程や保護膜形成工程を従来技術をそのまま
適用して半導体装置を実現することができる。ここでエ
アブリッジ構造のフォトレジスト膜33を除去する工程
はガスプラズマによるエツチングであり、組立工程の中
で基板表面に接触する必要がなくなる時点まで絶縁膜3
3を残しておくこともできる。これによりエアブリッジ
が損傷して歩留りが低下するという問題が解決できる。
Thereafter, a semiconductor device can be realized by applying conventional techniques to assembly processes such as back polishing, scribing, separating, bonding, etc., and protective film forming processes. Here, the step of removing the photoresist film 33 with the air bridge structure is etching using gas plasma, and the insulating film 3 is removed until it no longer needs to contact the substrate surface during the assembly process.
You can also leave 3. This solves the problem that the air bridge is damaged and the yield is reduced.

実施例では絶縁膜38にフォトレジストを用いたが、5
00℃以下で、かつできるだけ低温側で軟化し、ガスプ
ラズマで除去できる材料であれば本発明の要件を満たす
ものであり、何らフォトレジストに制限されるものでな
い。
In the example, photoresist was used for the insulating film 38, but 5
Any material that can be softened at temperatures as low as 00° C. or lower and can be removed by gas plasma satisfies the requirements of the present invention, and is not limited to photoresist in any way.

発明の効果 本発明によりエアブリッジの欠点であった段差切れ、機
械的強度の弱さからくる工程上の制約等が一挙に解決で
きエアブリッジの歩留りを大きく向上させることができ
る。     □
Effects of the Invention According to the present invention, the disadvantages of air bridges, such as step breakage and process constraints due to weak mechanical strength, can be solved at once, and the yield of air bridges can be greatly improved. □

【図面の簡単な説明】[Brief explanation of drawings]

図1はエアブリッジ構造の一例、図2は本発明の実施例
の一例である。図3(A)、(B)、(C)、■)はそ
の製作工程図である。 11.21.31・・・下側の配線 12.22.32・・・上側の配線 23.33・・・絶縁膜
FIG. 1 shows an example of an air bridge structure, and FIG. 2 shows an example of an embodiment of the present invention. Figures 3 (A), (B), (C), and ■) are manufacturing process diagrams. 11.21.31...Lower wiring 12.22.32...Upper wiring 23.33...Insulating film

Claims (1)

【特許請求の範囲】[Claims] (1)集積回路の多層配線技術のうち下側と上側の配線
金属が絶縁膜を介さずに立体交叉するエアブリッジ法に
おいて、500℃以下の高温で軟化する絶縁性材料で下
層配線をおおい、この後上層配線を形成し、該絶縁性材
料をガス・プラズマで除去することを特徴とする多層配
線方法。
(1) In the air bridge method, which is a multilayer wiring technology for integrated circuits in which lower and upper wiring metals intersect three-dimensionally without an insulating film, the lower wiring is covered with an insulating material that softens at a high temperature of 500°C or less. A multilayer wiring method characterized in that an upper layer wiring is then formed and the insulating material is removed by gas plasma.
JP2829283A 1983-02-21 1983-02-21 Multilayer interconnection method Pending JPS59152647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2829283A JPS59152647A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2829283A JPS59152647A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Publications (1)

Publication Number Publication Date
JPS59152647A true JPS59152647A (en) 1984-08-31

Family

ID=12244533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2829283A Pending JPS59152647A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Country Status (1)

Country Link
JP (1) JPS59152647A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01145133U (en) * 1988-03-28 1989-10-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01145133U (en) * 1988-03-28 1989-10-05

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