JPS59152648A - Multilayer interconnection method - Google Patents

Multilayer interconnection method

Info

Publication number
JPS59152648A
JPS59152648A JP2829383A JP2829383A JPS59152648A JP S59152648 A JPS59152648 A JP S59152648A JP 2829383 A JP2829383 A JP 2829383A JP 2829383 A JP2829383 A JP 2829383A JP S59152648 A JPS59152648 A JP S59152648A
Authority
JP
Japan
Prior art keywords
film
insulating film
air bridge
wiring
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2829383A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2829383A priority Critical patent/JPS59152648A/en
Publication of JPS59152648A publication Critical patent/JPS59152648A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve the yield and the reliability of an air bridge by protecting the lower layer wirings of a crossover by an insulating film, thereby eliminating a shortcircuit of upper and lower wirings and eliminating a stepwise disconnection or a restriction in the stage of works. CONSTITUTION:Upper layer wirings 22 cross lower layer wirings 21 through an insulating film 23 having a smooth section and an insulating film 24 under the film 23. The film 23 is etched by gas plasma which does not affect the influence to a substrate, wiring metal and the film 24, thereby forming an air bridge in noncontact. After lower layer wiring metal 31 is formed by normal photolithographic and lift-off methods, a nitrided silicon film 34 is formed, and a photoresist (OFPR-800) is formed on the entire substrate. A resist film 22 is allowed to remain only on the crossover of the upper and lower layer wirings for forming the air bridge by lithography. A lower insulating film pattern 34 is formed by plasma etching with CF4 gas. When it is baked at 200 deg.C for 20min, the resist is flowed to form a semispherical shape by the surface tension. Then, upper layer wirings 32 are formed. The film 33 of air bridge structure is removed by plasma etching with oxygen gas.

Description

【発明の詳細な説明】 技術分野 本発明は半導体基板上にトランジスタ、抵抗、コイル、
コンデンサ等の電子部品を形成し相互に接続したいわゆ
る集積回路の構造製造技術に関するものである。
[Detailed Description of the Invention] Technical Field The present invention provides transistors, resistors, coils, etc. on a semiconductor substrate.
The present invention relates to structural manufacturing technology for so-called integrated circuits in which electronic components such as capacitors are formed and interconnected.

背景技術 集積回路の動作速度を高速化し、かつ低消費電力化を図
る1には素子の微細化回路の高集積度化が必須である。
BACKGROUND ART In order to increase the operating speed of integrated circuits and reduce power consumption, it is essential to miniaturize elements and increase the degree of integration of circuits.

これに伴ない各部品及びそれらを相互に接続するための
配線が近接し、さらに配線間の交叉部が増加することに
なる。
As a result, each component and the wires for connecting them to each other are brought closer to each other, and the number of intersections between the wires increases.

その結果、とくに配線容量が増加し、動作速度の低減に
つながる。これを防ぐために有効な配線間の絶縁法が必
要となる。特に、マイクロ波以上の高周波域ではこの配
線容量の低減化が特性向上のために不可欠の課題となる
As a result, the wiring capacitance in particular increases, leading to a reduction in operating speed. To prevent this, an effective method of insulating the wiring is required. Particularly in the high frequency range of microwaves or higher, reducing the wiring capacitance is an essential issue for improving characteristics.

このような目的に対する有効な手段にエアブリッジ法が
ある。これは図1に示すように集積回路内において下側
の金属配線と上側の金属配線とが交叉する場合に両者間
に絶縁膜を介さず上側の配線金属が立体交叉する一層配
線技術である。この方法の特徴は2種の配線は比誘電率
の最も小さい空気で絶縁されているため他の任意の絶縁
膜を用いる場合に比して両配線間の容量が最も小さくな
ることにある。このなめ回路内の配線容量が低減され集
積回路の動作速度が改善される。・しかしながらエアブ
リッジは構造上上層配線が中空に浮いた状態にあり、エ
アブリッジ形成後は表面に接触する°ことができなくな
る。このため、以後の工程において以下のような様々な
技術的問題点・制約が生じる。
The air bridge method is an effective means for achieving this purpose. This is a one-layer wiring technology in which, as shown in FIG. 1, when lower metal wiring and upper metal wiring intersect in an integrated circuit, the upper metal wiring intersects three-dimensionally without intervening an insulating film between the two. The feature of this method is that since the two types of wiring are insulated by air having the lowest dielectric constant, the capacitance between the two wirings is the smallest compared to the case where any other insulating film is used. The wiring capacitance within this diagonal circuit is reduced and the operating speed of the integrated circuit is improved.・However, due to the structure of the air bridge, the upper layer wiring is suspended in the air, and after the air bridge is formed, it is no longer possible to contact the surface. For this reason, various technical problems and restrictions as described below arise in subsequent steps.

すなわち ■)高周波特性向上のため基板厚さを裏面から薄くする
場合、化学エツチングに必要な保護膜の形成が必要であ
る。一方、機械的研磨によって基板を薄くする場合基板
表面に接触する必要がある。
In other words, ①) When thinning the substrate from the back side in order to improve high frequency characteristics, it is necessary to form a protective film necessary for chemical etching. On the other hand, when thinning a substrate by mechanical polishing, it is necessary to contact the substrate surface.

2)基板上に多数繰り返して形成された半導体装置1−
tillしチップ化するスクライブ、セパレートの工程
では表面に破片や汚れが付着したり傷を付けたりするこ
とを防ぐために裏面から加工処理に施すことが多く必然
的に表面に接触することになる。
2) Semiconductor device 1- repeatedly formed on a substrate in large numbers
In the scribing and separating processes that produce chips by tilling, processing is often performed from the back side to prevent debris or dirt from adhering to the surface or causing scratches, and the process inevitably comes into contact with the front surface.

3)チップ化した半導体装置を一つずつパッケージへ装
着するボンディング工程ではコレットや真空ピンセット
にてチップ表面側を吸着することになる。
3) In the bonding process in which chipped semiconductor devices are attached to a package one by one, the surface side of the chip is attracted using a collet or vacuum tweezers.

4)最終的に集積回路に保護膜を形成す、る場合、外部
へ電気的接続をとり出すため保護膜に開口部を設ける。
4) When a protective film is finally formed on the integrated circuit, an opening is provided in the protective film in order to take out electrical connections to the outside.

ここで通常のコンタクト露光によるホトリソグラフィを
適用する場合、基板表面はホトマスクに強く密着される
ことになる。
If photolithography using normal contact exposure is applied here, the substrate surface will be tightly adhered to the photomask.

以上の工程まなは取扱いはエアブリッジを保護するとい
う点からは実施できないものであり、上述と同等の工程
を実施するためには煩雑な工程を附加することになる。
The above process cannot be carried out from the viewpoint of protecting the air bridge, and in order to carry out the same process as the above, a complicated process will be added.

この場合、半導体装置の生産性、歩留りが著しく悪化す
るという問題点が生じる。
In this case, a problem arises in that the productivity and yield of semiconductor devices are significantly deteriorated.

一方、エアブリッジ自身、溝造的に弱いものであり虜か
の外力によっても上層配線が切れたり、下層配線と接触
することが多く歩留りが低いという問題がある。また、
配線間の接触分防ぐため上層配線をできるだけ高い位置
に形成することが多く段差切れの危険がある。
On the other hand, the air bridge itself has a weak structure, and there is a problem in that the upper layer wiring is often broken or comes into contact with the lower layer wiring due to external force, resulting in a low yield. Also,
In order to prevent contact between wires, the upper layer wires are often formed as high as possible, creating a risk of step breakage.

発明の開示 本発明は上記従来技術の問題点を解決する新しい多層配
線方法分提供するものである。
DISCLOSURE OF THE INVENTION The present invention provides a new multilayer wiring method that solves the problems of the prior art described above.

以下実・施列に即して説明する。The following will explain the implementation/implementation.

図2′は本発明の実施例の一例を示すためのものであり
、滑らかな断面ともつ絶縁膜23及びその下の絶縁膜2
4を介して上゛層形線22が下層配線21と交叉してい
るものである。絶縁膜23を基板や配線金属や絶縁膜2
4に影響しないガスプラズマでエツチングすることによ
り非接触でエアブリッジが形成できる。以下エアブリッ
ジの製作工程の一例に図3に沿って説明する。
FIG. 2' is for showing an example of an embodiment of the present invention, and shows an insulating film 23 with a smooth cross section and an insulating film 2 below it.
4, the upper layer wire 22 intersects with the lower layer wiring 21. The insulating film 23 is connected to a substrate, wiring metal, or insulating film 2.
An air bridge can be formed without contact by etching with a gas plasma that does not affect etching. An example of the air bridge manufacturing process will be described below with reference to FIG. 3.

通常のフォI・リングラフィとリフトオフ法によって下
層の配線金属31を形成した後、プラズマCVD法で厚
さ0.3μmの窒化シリコン膜34f:形成し基板全面
に回転塗布法によりフォトレジス) (OFPR−8o
o)を2,5μmの厚さに形成する。
After forming the lower wiring metal 31 by ordinary photolithography and lift-off method, a silicon nitride film 34f with a thickness of 0.3 μm is formed by plasma CVD method, and photoresist (OFPR) is formed on the entire surface of the substrate by spin coating method. -8o
o) is formed to a thickness of 2.5 μm.

リソグラフィによってエアブリッジを形成する上層・下
層配線の交叉部とその周辺の領域にのみレジスト膜33
を残す。(図3−(5))CF4ガスのプラズマエツチ
ングにより上層の絶縁膜33をこのままでマスクとして
下側の絶縁膜パターン34.2形成する。(図3−(B
))この後、200°Cの温度で20分間ベークした。
A resist film 33 is applied only to the intersection of upper and lower layer interconnections and the surrounding area where air bridges are formed by lithography.
leave. (FIG. 3-(5)) A lower insulating film pattern 34.2 is formed using the upper insulating film 33 as a mask by plasma etching using CF4 gas. (Figure 3-(B
)) This was followed by baking at a temperature of 200°C for 20 minutes.

この時の温度はレジストが軟化する温度より十分高温で
ある泥めレジストカマ流れ表面張力にょって半球状の形
状となる。(図3−(C1)次いで、下層配線と同等′
の方法により上層配線32全形成する。(図3−(Dl
) 絶縁膜33の断面は軟化して殆んど円に近い状態である
ため上層配線が絶縁膜の段差部で断線するいわゆる段差
切れが解消できる。
The temperature at this time is sufficiently higher than the temperature at which the resist softens, and the muddy resist flows into a hemispherical shape due to surface tension. (Figure 3-(C1) Next, the same as the lower layer wiring'
The entire upper layer wiring 32 is formed by the method described in (a). (Figure 3-(Dl
) Since the cross section of the insulating film 33 is softened and almost circular, it is possible to eliminate so-called step breakage in which the upper layer wiring is broken at the step part of the insulating film.

続いて酸素ガスによるプラズマエツチングによりエアブ
リッジ構造のフォトレジスト膜33′f!:除去し、図
3−@に示すような交叉部の下層配線が絶縁膜で保護さ
れたエアブリッジを得る。以後、裏面研磨、スクライブ
、七バレート、ボンディング等の組立工程や保護膜形成
工程を従来技術をそのまま適用して半導体装置を実現す
ることができる。
Subsequently, the photoresist film 33'f! having an air bridge structure is formed by plasma etching using oxygen gas. :Removed to obtain an air bridge in which the lower wiring at the intersection is protected by an insulating film as shown in Figure 3-@. Thereafter, a semiconductor device can be realized by applying conventional techniques to the assembly processes such as back polishing, scribing, seven-barrelation, bonding, etc., and the protective film forming process.

ここで、エアブリッジ構造の7オトレジスト膜33を除
去する工程はガスプラズマによるエツチングであり、組
立工程の中で基板表面に接触する必要がなくなる時点ま
で絶縁膜33を残しておくこともできる。これによりエ
アブリッジが損傷して歩留りが低下するという問題が解
決できる。実施例では絶縁膜33にフォトレジストを用
いたが、500°C以下で、かつできるだけ低温側で軟
化しガスプラズマで絶縁膜34に対して選択的に除去で
きる材料であれば本発明の要件を満たすものであり、何
らフォトレジストに制限されるものでない。
Here, the step of removing the photoresist film 33 of the air bridge structure is gas plasma etching, and the insulating film 33 can be left until it is no longer necessary to contact the substrate surface during the assembly process. This solves the problem that the air bridge is damaged and the yield is reduced. In the embodiment, photoresist was used for the insulating film 33, but any material that softens at temperatures as low as 500°C or lower and can be selectively removed from the insulating film 34 using gas plasma can meet the requirements of the present invention. and is not limited to photoresist in any way.

また、絶縁膜34は形成または除去する工程において絶
縁膜33と互いに独立して加工処理できれば本発明の目
的を満たすものであり、材料としては、窒化シリコンに
何ら限定されるものでなく例えば有機樹脂膜、ポリイミ
ド樹脂、酸化シリコン、酸化アルミナ等の無機化合物膜
を用いることもできる。
Further, the object of the present invention is satisfied if the insulating film 34 can be processed independently from the insulating film 33 in the process of forming or removing it, and the material is not limited to silicon nitride, but may be made of, for example, an organic resin. Inorganic compound films such as films, polyimide resins, silicon oxides, and alumina oxides can also be used.

発明の効果 本発明は、交叉部の下層配線が絶縁膜で保護されたエア
ブリッジを形成するものであり、上層配線の機械的強度
が不十分なために生じる上下配線の短絡をなくすことが
でき、さらに、上層の絶縁膜を軟化させ、かつ非接触で
ガスプラズマエツチングすることにより段差切れや工程
上の制約を無くすることができ、エアブリッジの歩留り
、信頼性の向上が実現できる。
Effects of the Invention The present invention forms an air bridge in which the lower layer wiring at the intersection is protected by an insulating film, and it is possible to eliminate short circuits between the upper and lower wirings that occur due to insufficient mechanical strength of the upper layer wiring. Furthermore, by softening the upper insulating film and performing non-contact gas plasma etching, it is possible to eliminate step cuts and process constraints, and it is possible to improve the yield and reliability of the air bridge.

【図面の簡単な説明】[Brief explanation of drawings]

図1はエアブリッジ構造の一例、図2は本発明の実施例
の一例であり、図3(5)(B) (C) D(5)は
その製作工程を説明するための図である。 11、21.81・・・・・・下側の配線12・22.
32・・・・・・・上側の配線23・33・・・・・・
・・・・・・・・L側の絶縁膜24.34・・・・・・
・・・・・・・・・下側り絶縁膜図N 図2 図3
FIG. 1 is an example of an air bridge structure, FIG. 2 is an example of an embodiment of the present invention, and FIGS. 3(5), (B), (C), and D(5) are diagrams for explaining the manufacturing process thereof. 11, 21.81... Lower wiring 12, 22.
32... Upper wiring 23, 33...
......L side insulating film 24.34...
・・・・・・Lower insulation film diagram N Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 (1)集積回路の多層配線技術のうち上側と下側の′配
線金属が絶縁膜を介さずに立体交叉するエアブリッジ法
において、上側と下側の配線の交叉部の下層配線が絶縁
膜でおおうようにしたことを特徴−とする多層配線方法
。 ・(2)互いに選択的に除去できる二種類の膜からなる
絶縁性材料で下層配線及び交叉部をおおい、この後上層
配線を形成し、さらに上層の絶縁膜材料□のみを除去し
てエアブリッジとすることを特徴とする特許請求の範囲
第1項記載の多層配線方法。 (3)二種類の絶縁膜のうち上層の絶縁膜が500°C
以下の温度で軟化しかつガスプラズマで除去できる材料
であることを特徴とする特許請求の範囲第2項記載の多
層配線方法。
[Scope of Claims] (1) Among multilayer wiring technologies for integrated circuits, in the air bridge method in which the upper and lower wiring metals cross three-dimensionally without intervening an insulating film, the intersection of the upper and lower wirings is A multilayer wiring method characterized in that the lower layer wiring is covered with an insulating film.・(2) Cover the lower layer wiring and the intersection with an insulating material consisting of two types of films that can be selectively removed from each other, then form the upper layer wiring, and then remove only the upper layer insulation film material □ to form an air bridge. A multilayer wiring method according to claim 1, characterized in that: (3) The temperature of the upper layer of the two types of insulation films is 500°C.
3. The multilayer interconnection method according to claim 2, wherein the material is softened at a temperature below and can be removed by gas plasma.
JP2829383A 1983-02-21 1983-02-21 Multilayer interconnection method Pending JPS59152648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2829383A JPS59152648A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2829383A JPS59152648A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Publications (1)

Publication Number Publication Date
JPS59152648A true JPS59152648A (en) 1984-08-31

Family

ID=12244564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2829383A Pending JPS59152648A (en) 1983-02-21 1983-02-21 Multilayer interconnection method

Country Status (1)

Country Link
JP (1) JPS59152648A (en)

Similar Documents

Publication Publication Date Title
JPH07183325A (en) Bonding pad including circular exposed region and preparation thereof
US7575980B2 (en) Semiconductor device and method for manufacturing the same
US6348398B1 (en) Method of forming pad openings and fuse openings
US20120280399A1 (en) Buffer pad in solder bump connections and methods of manufacture
US7393774B2 (en) Method of fabricating microconnectors
US20030171001A1 (en) Method of manufacturing semiconductor devices
JPS59152648A (en) Multilayer interconnection method
JPH0465540B2 (en)
KR20010102317A (en) Pad metallization over active circuitry
JPS59155947A (en) Multilayer interconnection method
JPS59152647A (en) Multilayer interconnection method
KR20120106604A (en) Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer
KR100556351B1 (en) Metal Pad of semiconductor device and method for bonding of metal pad
KR940007290B1 (en) Manufacturing method of wirebonding pad
CN109830459B (en) Method for forming fuse structure
JP2000232092A (en) Manufacture of semiconductor device and semiconductor device
JPH04316339A (en) Manufacture of semiconductor device
CN117766511A (en) Fuse structure and preparation method thereof, semiconductor integrated circuit and preparation method thereof
JPH04287326A (en) Semiconductor device and its manufacture
JPS59149098A (en) Semiconductor device
KR19980052423A (en) Semiconductor device manufacturing method
JPH0282555A (en) Semiconductor device
KR100712815B1 (en) Method of implementing the sinter process in the semiconductor
JP2003204032A (en) Electronic component and its manufacturing method
KR100604775B1 (en) Method for Treating Edge of Semiconductor Wafer