JPS59149023A - Method for introduction of impurity into semiconductor - Google Patents

Method for introduction of impurity into semiconductor

Info

Publication number
JPS59149023A
JPS59149023A JP2393783A JP2393783A JPS59149023A JP S59149023 A JPS59149023 A JP S59149023A JP 2393783 A JP2393783 A JP 2393783A JP 2393783 A JP2393783 A JP 2393783A JP S59149023 A JPS59149023 A JP S59149023A
Authority
JP
Japan
Prior art keywords
layer
impurity
heat treatment
semiconductor
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2393783A
Other languages
Japanese (ja)
Inventor
Yoshinari Matsumoto
松本 良成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2393783A priority Critical patent/JPS59149023A/en
Publication of JPS59149023A publication Critical patent/JPS59149023A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To contrive improvement in reproducibility of impurity introduction by a method wherein a crystal layer, having the degree of resolution of introduced impurities smaller than that of an impurity introduction semiconductor, is formed on the surface of a compound semiconductor whereon impurities will be introduced. CONSTITUTION:A heterogeneous semiconductor layer AlGaAs thin film 12 is formed in advance on the surface of a GaAs wafer 11 as a compound semiconductor crystal by performing an epitaxial growing method using an MOCVD method or an MBE method. Subsequently, an ion-implanted layer 21 is provided by implanting Zn. Then, after an Si3N4 layer 31 has been formed on the AlGaAs layer 12 by performing a vapor-phase growing method, a high density Zn diffusion layer 32' is formed by performing a heat treatment at 800 deg.C for 20min in GaAs11. When the Si3N4 film 31 is removed using HF after performance of a heat treatment and subsequently an AlGaAs layer 12 is removed, the etching by HF is automatically stopped on the surface of the GaAs11, thereby enabling to obtain the compound semiconductor layer having a Zn diffusion layer on the surface.

Description

【発明の詳細な説明】 本発明は半導体への不純物の導入方法に関する◎1[−
V族化合物に代表される化合物半導体へ不純物を導入す
る技術を再現性と制御性に優れたものにすることは一般
に困難である。何故ならばG a A s結晶等の化合
物半導体はイオン注入等によシ結晶中に損傷等が発生し
やすく、イオン注入後熱処理においても表面熱分解等が
生じ易いためである。
[Detailed Description of the Invention] The present invention relates to a method for introducing impurities into a semiconductor.
It is generally difficult to develop techniques for introducing impurities into compound semiconductors, such as group V compounds, with excellent reproducibility and controllability. This is because compound semiconductors such as GaAs crystals are easily damaged by ion implantation, etc., and surface thermal decomposition is also likely to occur during heat treatment after ion implantation.

A/203 膜等を付着させ、化合物半導体の熱分解に
よシ表面非化学量論的欠陥の発生を極力おさえる方策が
とられる。しかし、8i02,8iaN4゜Al2O3
等をCVD成長する場合にも化合物半導体結晶を高温(
300° 700°C)にする必要があシ、この際、表
面近くに化学量論的欠陥が発生する。
A/203 Measures are taken to suppress the occurrence of surface non-stoichiometric defects as much as possible by attaching a film or the like and thermally decomposing the compound semiconductor. However, 8i02, 8iaN4゜Al2O3
When growing compound semiconductor crystals by CVD, etc., compound semiconductor crystals are grown at high temperatures (
300° to 700°C), at which time stoichiometric defects occur near the surface.

またこれら8 i02. a l 1IN4あるいはA
A’203等の膜(以後阻止膜と呼ぶ)と化合物半導体
結晶との界面を制御することは極めて難かしい。特にG
aAs等のイオン注入で通常行なわれているように、G
aAs表面を露出したままイオン注入すると、注入層は
〜1000A内外かので表面エツチング等を十分性なう
ことができず、前記阻止膜を表面に形成しなければなら
ないため阻止膜と化合物半導体結晶の界面を制御すると
とは困難である。
Also these 8 i02. a l 1IN4 or A
It is extremely difficult to control the interface between a film such as A'203 (hereinafter referred to as a blocking film) and a compound semiconductor crystal. Especially G
As is commonly done in ion implantation such as aAs, G
If ions are implanted with the aAs surface exposed, the implantation layer will be around ~1000A, so surface etching etc. cannot be performed sufficiently, and the above-mentioned blocking film must be formed on the surface, so the barrier film and the compound semiconductor crystal will be separated. Controlling the interface is difficult.

以上述べたこと等の原因のためにGaAs等へのイオン
注入およびその後の熱処理によシネ細物導入に関して再
現性の向上を果すことは極めて困難である。
Due to the reasons mentioned above, it is extremely difficult to improve the reproducibility of ion implantation into GaAs or the like and the introduction of cine fine particles through subsequent heat treatment.

本発明は化合物半導体へイオン注入して不純物を導入す
る場合に、前記問題点を除去し、再現性にすぐれた不純
物導入方法を提供することにある・不発明によるならば
不純物導入層の再現性の高い製造はもとよシ、イオン注
入および熱処理等の活性化段階で終了する不純物導入後
のプロセス前での表面処理をも極めて確集にしがも清浄
に行なうことが可能となる0本発明の不純物導入方法を
用いることKよシ、デバイス・プロセスの安定化、出来
上ったデバイスの信頼性に関して著しい向上をもたらす
The purpose of the present invention is to eliminate the above-mentioned problems when introducing impurities into a compound semiconductor by ion implantation, and to provide an impurity introduction method with excellent reproducibility. The present invention makes it possible not only to produce high quality products, but also to perform surface treatment very accurately and cleanly before the process of introducing impurities, which ends at the activation stage such as ion implantation and heat treatment. Using this impurity introduction method significantly improves the stability of the device process and the reliability of the resulting device.

不発明によると不純物を導入すべき化合物半導体表面上
に前記導入不純物の溶解度が前記被不純物導入半導体に
対するよシも小さい結晶層をエピタキシャル成長する工
程と、このエピタキシャル成長した表面、もしくは前記
エピタキシャル成長表面上に形成された熱処理用保護膜
表面よシネ細物を導入する工程と、熱処理を加えること
によシ前記導入不純物を被不純物導入半導体に移動させ
る工程と、前記4被不純物導入半導体上に形成したエピ
タキシャル層を除去する工程とを含むことを特徴とする
半導体への不純物の導入方法が得られる。
According to the invention, a step of epitaxially growing a crystal layer on the surface of a compound semiconductor into which an impurity is to be introduced, in which the solubility of the introduced impurity is smaller than that of the semiconductor to be introduced with the impurity, and forming a crystal layer on this epitaxially grown surface or on the epitaxially grown surface. a step of introducing a cine fine substance into the surface of the protective film for heat treatment, a step of transferring the introduced impurity to the semiconductor to be impurity-introduced by applying heat treatment, and an epitaxial layer formed on the semiconductor to be impurity-introduced. A method for introducing impurities into a semiconductor is obtained, the method comprising the step of removing.

以下、本発明をGaAsへのZnのイオン注入による不
純物導入の場合について実施例をもとに詳細に説明する
Hereinafter, the present invention will be explained in detail based on an example, regarding the case of impurity introduction by Zn ion implantation into GaAs.

第1図よシ第3図は不発明の一実施例を工程順に説明す
る図で、第1図は不純物を導入しようとする化合物半導
体結晶としてGaAsウェーハ11、その表面にあらか
じめ異種半導体層AA!GaAsAlGaAs薄膜方法
、例えばMOCVD法あるいはMBE法でエピタキシャ
ル成長した断面を示しである。この後、第2図に示すよ
うにイオン注入層21を設ける。イオン注入層としては
Znを用い5QKeVの加速でイオン注入量Nsとして
2X10”鋼 を導入した例を示す。AAtGaAs層
12の厚みを実施例では200OAとしたので、イオン
注入層21の厚みはAJGaAa 層12の厚さの約1
/2である。なお実施例におけるAA!GaAsAlG
aAs層12の組成比は0.5:O15であシ、導入不
純物Znの溶解度がGaAsのZnの溶解度よシも小さ
くなっている。
Figures 1 to 3 are diagrams explaining an embodiment of the invention in the order of steps. Figure 1 shows a GaAs wafer 11 as a compound semiconductor crystal into which impurities are to be introduced, and a foreign semiconductor layer AA! This is a cross section of a GaAsAlGaAs thin film grown epitaxially by a method such as MOCVD or MBE. After this, an ion implantation layer 21 is provided as shown in FIG. An example is shown in which Zn is used as the ion implantation layer and 2X10'' steel is introduced with an acceleration of 5QKeV and an ion implantation amount Ns.Since the thickness of the AAtGaAs layer 12 is 200OA in the example, the thickness of the ion implantation layer 21 is the same as the AJGaAa layer. Approximately 1 in 12 thickness
/2. Note that AA! in Examples! GaAsAlG
The composition ratio of the aAs layer 12 is 0.5:O15, and the solubility of the introduced impurity Zn is smaller than that of Zn in GaAs.

この後AlGaAs5層12上に第3図の断面に示すよ
うに8 i 3N4層31を気相成長法で200OA厚
で形成後、800℃で20分の熱処理を加えた後には注
入不純物層は第3図32で示すように広がるO この熱処理後の注入ZnKよるアクセプタ濃度を室温で
測定した0第4図にはAlGaAs 層120表面から
測定したアクセプタ濃度の深さ方向分布を示す。第4図
で見るようにAlGaAs  12と5− GaAsウェーハ11の界面を境にアクセプタ濃度の段
差が明瞭に見られる。AlGaAs 12側でのアクセ
プタ濃度は〜8X10 cm  であるのに対し、G 
a A sウェーハ11側では1.2X10 an  
 となっている。
Thereafter, as shown in the cross section of FIG. 3, an 8i3N4 layer 31 was formed on the AlGaAs5 layer 12 to a thickness of 200 OA by vapor phase epitaxy, and after heat treatment at 800°C for 20 minutes, the implanted impurity layer was removed. 3. As shown in FIG. 32, the acceptor concentration due to the implanted ZnK was measured at room temperature after this heat treatment. FIG. 4 shows the depth distribution of the acceptor concentration measured from the surface of the AlGaAs layer 120. As shown in FIG. 4, a difference in acceptor concentration can be clearly seen at the interface between the AlGaAs 12 and the 5-GaAs wafer 11. The acceptor concentration on the AlGaAs 12 side is ~8X10 cm, whereas the G
a A s 1.2X10 an on the wafer 11 side
It becomes.

熱処理後に第4図のようrgアクセプタ濃度分布と々る
ことは次のように定性的に説明できる。まずZnイオン
注入量N5=10 cm  はAlGaAs層12にお
けるZnの溶解度(熱処理温度800°Cでの)を約1
桁以上越えるものである。従って、800°Cの熱処理
を加えた時、注入されたZnはAA!GaAsAlGa
As層12除される如く拡散する。Znの拡散はSI!
lN4膜21中では極めて生じ難く、必然的にGaAs
1l中にZni排除される。この熱処理により急速KA
A!GaAs層12よシ排除されたZnがGaAs1I
中での高濃度のZn拡散膚32′を与えると考えること
がで負る。高濃度Zn拡散層32′の厚さは実施例に示
した第4図の結果を与える800°020分の熱処理で
は〜1000Aで再現性良く得られる。
The fact that the rg acceptor concentration distribution fluctuates as shown in FIG. 4 after heat treatment can be qualitatively explained as follows. First, the Zn ion implantation amount N5 = 10 cm increases the solubility of Zn in the AlGaAs layer 12 (at a heat treatment temperature of 800°C) by approximately 1.
This is more than an order of magnitude higher. Therefore, when heat treatment is applied at 800°C, the implanted Zn becomes AA! GaAsAlGa
The As layer 12 is diffused as if removed. Zn diffusion is SI!
It is extremely difficult to form in the lN4 film 21, and inevitably GaAs
Zni is excluded in 1 l. This heat treatment results in rapid KA
A! The Zn removed from the GaAs layer 12 becomes GaAs1I.
It can be considered that a high concentration of Zn diffuses in the skin 32'. The thickness of the high concentration Zn diffusion layer 32' can be obtained with good reproducibility at ~1000 A by heat treatment at 800 DEG 020 minutes giving the results shown in FIG. 4 shown in the example.

6− との良好な再現性はZnの拡散にとって関与する界面が
GaAs11とA/GaAs12のへテロ半導体接合界
面であシ、良好な結晶学的つなか!llをも濃度は低下
しかつ、その厚さは増加するととは定性的考察によって
も容易に理解できるとうシである。このように熱処理時
間と温度の設定により再現性良(GaAsll中にZn
不純物導入層32′が得られる。
The good reproducibility with 6- is because the interface involved in Zn diffusion is the hetero semiconductor junction interface of GaAs11 and A/GaAs12, which has a good crystallographic connection! It can be easily understood from a qualitative consideration that the concentration also decreases and the thickness increases. In this way, by setting the heat treatment time and temperature, the reproducibility was good (Zn in GaAs
An impurity-introduced layer 32' is obtained.

従来技術でGaAs中にZniイオン注入して熱処理す
る場合にはZnをイオン注入層にその注入表面Vr、5
to2膜や、S i 8N4膜を付着しGaAs表入− 面の熱分解を防止、かつ、Znの外部への飛散を防ぎ、
5iOz膜の場合SOO″C+ 8 i 3 N 4 
 膜の場合〜850°Cで約20公租度熱処理を行なっ
ている。
In the conventional technique, when Zni ions are implanted into GaAs and heat treated, Zn is added to the ion implantation layer at its implantation surface Vr, 5.
To2 film or Si8N4 film is attached to prevent thermal decomposition of the GaAs surface and to prevent Zn from scattering to the outside.
For 5iOz film SOO″C+ 8 i 3 N 4
In the case of membranes, heat treatment is performed at ~850°C for about 20 degrees.

この場合、熱処理後のZn注入層で活性化したZnアク
セプター濃度およびその分布は活性化率が低い、あるい
は低濃度不純物濃度ティルを生じる等の現象が見られ、
かつその再現性にも欠けるととが問題であった◎ しかるに不発明の方法によると極めて安定した再現性に
優れた不純物注入が達成できる。
In this case, phenomena such as a low activation rate or a low impurity concentration till are observed in the concentration and distribution of Zn acceptors activated in the Zn implanted layer after heat treatment.
Moreover, the problem was that the reproducibility was also lacking.◎However, the uninvented method can achieve impurity implantation that is extremely stable and has excellent reproducibility.

なお、前記した如く、AlGaAs12上に付着する膜
31としては熱処理時に母体構成元素を多量に溶融する
または透過するものではまらないが、前記した如く8i
sNa膜等を用いれば十分である。
As mentioned above, the film 31 attached on the AlGaAs 12 must not melt or permeate a large amount of host constituent elements during heat treatment, but as mentioned above, 8i
It is sufficient to use an sNa film or the like.

なぜなら、8i3N4膜は前記した如く、850°C程
度の熱処理では母体元素との何らかの反応を生じるが、
800℃程度以下の比較的低い温度で本発明の不純物導
入は達成されるので変質は問題とならたいからである。
This is because, as mentioned above, when the 8i3N4 film is heat-treated at about 850°C, some reaction occurs with the host element.
This is because the impurity introduction of the present invention is achieved at a relatively low temperature of about 800° C. or lower, so deterioration should not be a problem.

また、従来技術では不純物を導入使用する表面を露出し
てイオン注入するために、表面にハイドp・カーボン等
の付着が見られ、との表面に熱処理時には8i3N4膜
等を付着して活性化を行なうため、GaAs表面近傍層
すなわちイオン注入層自身の不純物汚染を椿めて管理す
ることがむずかしかった。
In addition, in the conventional technology, since the surface where impurities are introduced is exposed and ions are implanted, adhesion of hydride p, carbon, etc. is observed on the surface, and during heat treatment, an 8i3N4 film etc. is attached to the surface to activate it. Therefore, it is difficult to prevent and control impurity contamination in the layer near the GaAs surface, that is, in the ion-implanted layer itself.

しかるに本発明の不純物導入法においては、イオン注入
、熱処理後に実施例にて示すならばHFによp843N
a膜21、引続いてAA’GaAsAlGaAs12上
GaAs11表面にて自動的にHFによるエツチングは
停止し、清浄な表面が露出する。即ち、次のプロセスに
引きつがれる不純物Znの導入されたG a A s表
面は極めて清浄度の高いものとなシ、素子化プロセスの
安定度を増し、素子の製作歩留シの向上、出来上がった
素子の信頼性も高いものとなる。
However, in the impurity introduction method of the present invention, after ion implantation and heat treatment, p843N is
Etching by HF is automatically stopped on the surface of the GaAs 11 on the a film 21 and then on the AA'GaAsAlGaAs 12, and a clean surface is exposed. In other words, the surface of the GaAs introduced with the impurity Zn, which is carried over to the next process, has extremely high cleanliness, which increases the stability of the device fabrication process, improves the device manufacturing yield, and improves the finished product. The reliability of the device also becomes high.

以上、本発明f G a A aへZnを導入する場合
について詳細に述べたが、この発明は他の化合物半導体
例えばInPに格子整合のとれたI nGaA a混晶
などについても、ZnやCdを導入したシ(この場合A
lGaAsに代J)InPを用いるとよい。)する場合
にも適用できるもので、要は被不純物導入しようとする
化合物半導体上にエピタキシャルに成長した結晶層を作
シ、かつ導入不純物の溶解度が前者に較べ稜者結晶層で
小さいような組み合せが得られるものならばあらゆる化
合物半導体への不純物導入技術として用いることができ
る。また、9− 不純物についても限定されるものでないととは明らかで
ある。
The case where Zn is introduced into fGaAa of the present invention has been described in detail above, but this invention also applies to the introduction of Zn or Cd into other compound semiconductors such as InGaAa mixed crystals that are lattice-matched to InP. The installed system (in this case A
It is preferable to use InP instead of lGaAs. ), the key is to create a crystal layer epitaxially grown on the compound semiconductor into which impurities are to be introduced, and the solubility of the introduced impurities is smaller in the ridge crystal layer than in the former. If it can be obtained, it can be used as a technique for introducing impurities into any compound semiconductor. Furthermore, it is clear that there are no limitations regarding the 9- impurity.

不発明によるならば不純物導入層の再現性の高い製作は
もとよ)、イオン注入および熱処理等の活性化段階で終
了する不純物導入後のプロセス前での表面処理をも極め
て確実にしかも清浄に行なうことが可能となる。
In addition to highly reproducible production of impurity-introduced layers, the invention also makes surface treatment extremely reliable and clean before the process after impurity introduction, which ends in the activation stage such as ion implantation and heat treatment. It becomes possible to do so.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図および第3図は不発明による不純物の導
入方法の一実施例の工程順の説明断面図、第4図は不純
物導入完了時点での濃度の場所分布を示す。 11−・・・GaAa、 12−=AIGaAa層、2
1・・・・・・Znイオン注入層、31・・・・・・5
iBN4膜、32・・・・・・熱処理のZn導入層。 代理人 弁理士  内 原   晋 10− 幣2図 第3図 (表面)     S巨離(A) 第4図
FIGS. 1, 2, and 3 are cross-sectional views illustrating the steps of an embodiment of the impurity introduction method according to the invention, and FIG. 4 shows the location distribution of the concentration at the time when the impurity introduction is completed. 11-...GaAa, 12-=AIGaAa layer, 2
1...Zn ion implantation layer, 31...5
iBN4 film, 32... Zn introduction layer of heat treatment. Agent Patent Attorney Susumu Uchihara 10- Fig. 2 Fig. 3 (front) S Gyori (A) Fig. 4

Claims (1)

【特許請求の範囲】[Claims] 不純物の導入すべき化合物半導体表面上に前記導入不純
物の溶解度が前記被不純物導入半導体に対するよシも小
さい結晶層をエピタキシャル成長する工程と、このエピ
タキシャル成長した表面、もしくは前記エピタキシャル
成長表面上に形成された熱処理用保護膜表面よシネ細物
を導入する工程と、熱処理を加えることによシ前記導入
不純物を被不純物導入半導体に移動させる工程と、前記
被不純物導入半導体上に形成したエピタキシャル層を除
去する工程とを含むことを特徴とする半導体への不純物
の導入方法。
A step of epitaxially growing a crystal layer on the surface of a compound semiconductor into which an impurity is to be introduced, in which the solubility of the introduced impurity is smaller than that of the impurity-introduced semiconductor, and a process for heat treatment formed on the epitaxially grown surface or the epitaxially grown surface. a step of introducing a cine fine substance from the surface of a protective film; a step of moving the introduced impurity to the impurity-introduced semiconductor by applying heat treatment; and a step of removing an epitaxial layer formed on the impurity-introduced semiconductor. A method for introducing an impurity into a semiconductor, the method comprising:
JP2393783A 1983-02-16 1983-02-16 Method for introduction of impurity into semiconductor Pending JPS59149023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2393783A JPS59149023A (en) 1983-02-16 1983-02-16 Method for introduction of impurity into semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2393783A JPS59149023A (en) 1983-02-16 1983-02-16 Method for introduction of impurity into semiconductor

Publications (1)

Publication Number Publication Date
JPS59149023A true JPS59149023A (en) 1984-08-25

Family

ID=12124438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2393783A Pending JPS59149023A (en) 1983-02-16 1983-02-16 Method for introduction of impurity into semiconductor

Country Status (1)

Country Link
JP (1) JPS59149023A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721824A (en) * 1980-07-14 1982-02-04 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721824A (en) * 1980-07-14 1982-02-04 Fujitsu Ltd Manufacture of semiconductor device

Similar Documents

Publication Publication Date Title
JP2889589B2 (en) Method for manufacturing alternate layers of single crystal semiconductor material layer and insulating material layer
JP4854921B2 (en) Method of manufacturing a substrate by transferring a donor wafer containing foreign species and associated donor wafer
US4477308A (en) Heteroepitaxy of multiconstituent material by means of a _template layer
US5275687A (en) Process for removing surface contaminants from III-V semiconductors
US4960728A (en) Homogenization anneal of II-VI compounds
US4948751A (en) Moelcular beam epitaxy for selective epitaxial growth of III - V compound semiconductor
JPH0794494A (en) Manufacture of compound semiconductor device
JPS59149023A (en) Method for introduction of impurity into semiconductor
JPH04233219A (en) Manufacture of products comprising semiconductor devices
JP2735190B2 (en) Molecular beam epitaxy growth method and growth apparatus
JPH0831410B2 (en) Method for manufacturing semiconductor device
JPS62137821A (en) Vapor growth method for semiconductor
Rosner et al. Microstructure of thin layers of MBE-grown GaAs on Si substrates
JPH04199507A (en) Solid phase diffusion of n-type impurity to iii-v compound semiconductor
JPS63192227A (en) Epitaxial growth method of compound semiconductor
JPH0831426B2 (en) How to introduce impurities
JP2527227B2 (en) Semiconductor device and manufacturing method thereof
JPH05144727A (en) Manufacture of heteroepitaxial wafer
JPH05182910A (en) Molecular beam epitaxtially growing method
JPH01160899A (en) Method for growing compound semiconductor crystal and apparatus therefor
JPS63155608A (en) Method for epitaxial growth of compound semiconductor
JPS62145736A (en) Liquid phase epitaxial growth
JPH0262033A (en) Growth of compound semiconductor thin-film crystal
JPH07302740A (en) Gaas single crystal substrate for liquid phase epitaxial growth
JPH02237109A (en) Manufacture of semiconductor device