JPS62137821A - Vapor growth method for semiconductor - Google Patents

Abstract

PURPOSE:To obtain an excellent interface characteristic and to apply the advantage of vapor phase growing widely, by performing the vapor-phase growing of a second III-V semiconductor layer, which forms a lattice alignment with a first III-V semiconductor layer and includes other group V elements, on the III-V semiconductor layer including group V elements, and further performing the vapor-phase growing of a third III-V semiconductor layer, which forms lattice alignment with the second layer and include other group V elements. CONSTITUTION:An InP substrate 1 is kept at 650 deg.C, which is a growing temperature in PH3 gas. Under this state, AsH3 gas triehylindium (TEI) and triethylgallium (TEG) are introduced, and InGaAsP 3 is grown. The gas compositions at the time of the growing are PH3/AsH3approx.=4 and TEG/TEI=0.61. The composition of the growing layer has a difference in lattice constant of + or -0.1%. The growing time is 1min, and the thickness is 200Angstrom . Thereafter, the PH3 gas is stopped, and InGaAs 2, which undergoes lattice alignment by the gas ratio of TEC/TEI=0.89, is grown. Then, the growing layer having extremely excellent state of the surface, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for vapor phase growth of compound semiconductors, particularly group IV compound semiconductors.

Conventional technology Compared to liquid phase epitaxial growth, the vapor phase growth method for semiconductors can grow a much thinner growth layer with higher precision and uniformity, and there are no disadvantageous phenomena such as meltback. This is the most effective method of formation. Recently, quantum well lasers, high-performance field effect transistors, and the like have been realized using vapor phase growth technology in which thin layers of different compositions are grown alternately. The realization of such high-performance semiconductor devices relies heavily on semiconductor heterojunctions. Therefore, the growth technique is required to suppress the occurrence of defects at the Peter interface and to obtain a high-quality bonding surface.

Problems to be Solved by the Invention However, in compound semiconductors, the saturated vapor pressure of group V elements increases at high temperatures, so depending on the amount of raw material gas of group V elements, thermal decomposition is likely to occur, especially in compound semiconductors. V emission,
In the vapor phase growth of semiconductor heterojunctions made of different types of elements, it is unavoidable that a part of the grown layer is thermally decomposed when switching source gases, resulting in deterioration of crystallinity. For example, indium neighbored (
Ink) on arsenic indium gallium (InCaA)
s) In the case of f-growth, after completely removing phosphine (PH5), which is the raw material gas for P, from inside the growth apparatus,
Introducing arsine (AsH3), which is a raw material gas for As,
InGaAs must be grown, and part of the InP is thermally decomposed in a short period of time from the end of rnP growth to the start of InGaAs growth. On the other hand, AS is not properly removed before the PH3 gas is completely removed.
If an attempt is made to introduce H3 gas and start the growth of InGaAg, an InGaAsP intermediate layer whose composition cannot be controlled will be formed, and deterioration of crystallinity due to lattice misalignment will inevitably occur.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a first group (I)-v semiconductor layer containing at least one of the group (II) elements. Contains at least one group element and a group V element other than the group V element contained in the first group IV semiconductor layer, and is lattice matched with the first group M-V semiconductor layer. a step of vapor phase growing a second I-Vi semiconductor layer; and on the second m-v r, 33 semiconductor layer;
A step of growing a 30th ■-V group semiconductor layer in a vapor phase, which contains the group ■ element contained in the second ■-V group semiconductor layer and is lattice-matched with the second M-V group semiconductor layer. including.

According to the present invention, the growth of the intermediate layer can be started without stopping the Group V raw material gas for the first layer, and similarly, the structure of the intermediate layer V
While some of the group element gas is flowing to suppress thermal decomposition, the second
Thermal deterioration factors can be eliminated. Furthermore, since the composition of the intermediate layer is set to lattice match the first layer and the second layer, deterioration of crystallinity due to mechanical factors can be avoided.

EXAMPLE The method of the present invention is applied to a metal organic pyrolysis vapor phase epitaxy method for growing InGaAs f on InP, and a virtual array will be described below with reference to FIG. InP substrate 1 is PH3i1
% concentration of hydrogen gas, there is no change even after heat treatment at 650° C. for 1 hour, but in an atmosphere that does not contain PH5, thermal decomposition occurs even in a short time of about 1 to 2 minutes, forming In grains. For this reason, a high-quality surface could not be obtained by growing 1nGaAs directly on InP.

In the embodiment of the present invention, the InP substrate 1 is held at the growth temperature of 650'C in PH3 gas, and in this state, AsH
, gas and triethylindium (T]i:I),
By introducing triethyl gallium (TEG), InGaAs
Grew P3. The gas composition during growth was PI (3/A
SH,=4, Tel/TEI: 0.61,
The composition of the grown layer has a difference in lattice constant of ±0.1 fission or less. The growth time was 1 minute, and the thickness was about 200 mm.
It's a person. After that, stop the PH and gas, and TEG/TEI.
InGaA lattice-matched by a gas ratio of =0.89
When the layer was grown at 100 g2f, a grown layer with an extremely good surface condition was obtained.

FIG. 2 shows the results of examining the electron mobility at low temperature (77K) with respect to the thickness of the grown layer in order to fully quantitatively evaluate these results. When the InGaAs 1' intermediate layer is not provided, as shown by curve 5, as the thickness of the InGaAs layer becomes thinner, the mobility decreases, indicating that the adverse effect near the interface is large. On the other hand, when an InGaAsP intermediate layer is used, no such tendency is observed as shown in curve 4.
It was found that a good Peter interface was obtained.

Effects of the invention - According to the present invention, excellent interfacial properties can be obtained by a simple method even in the vapor phase growth of petrojunctions with different constituent group V elements, and the advantages of vapor phase growth can be applied more widely. It is expected to become, and its industrial value is a dog.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a heterojunction layer according to an embodiment of the present invention, and Figure 2 is a comparison of the relationship between InGaAs layer thickness and electron mobility obtained in an embodiment of the present invention with that of a conventional method. This is a diagram. 1...InP substrate, 2...InGaA
s growth layer, 3...InGaAsP intermediate layer, 4.
...Electron mobility of InGaAs layer obtained by the method of the present invention, 5...InGaAs layer obtained by conventional method
Electron mobility of the layer.

Claims (1)

[Claims] a first III- containing at least one group V element;
On the group V semiconductor layer, the first group V element and the first group
and at least one group V element other than the group V element contained in the III-V group semiconductor layer, and the first I
a step of vapor phase growing a second III-V group semiconductor layer that is lattice-matched to the II-V group semiconductor layer; The method is characterized by comprising a step of vapor phase growing a third group III-V semiconductor layer that includes a group V element contained in the layer and is lattice-matched with the second group III-V semiconductor layer. Semiconductor vapor phase growth method.