JPS59148191A - Memory driving circuit - Google Patents

Abstract

PURPOSE:To attain the high-speed access of an ambient system even with a low- speed memory by applying the present and past outputs of an address counter alternately to a memory. CONSTITUTION:The count value of an address counter 1 is updated with a clock CLK1, and the count address of the counter 1 is latched by a buffer register 2. Then the counter 1 is updated with the new value with a clock CLK2. The signal SEL to be applied to a selector 3 is synchronous with the CLK1 and has the larger pulse width than the CLK1. The selector 3 selects the latch output of the register 2 when the signal SEL is set at an H level and then selects the count address of the counter 1 when the signal SEL is set at an L level respectively. The output of the register 2 is turned into the past data which is delayed by a compared with the output of the counter 1. Thus the read/write access is carried out for a memory 4 with the output address of the selector 3.

Description

[Detailed description of the invention] The present invention relates to a memory drive circuit.

A conventional memory drive circuit has an address counter with 2 −
ff Therefore, address 7 is generated, and the configuration is such that this address is directly given as a memory address.

However, compared to the processing speed around Meq 11, Memo 1)
When the cycle time of the memory itself was slow, the circuits surrounding the memory were also changed to circuits that performed slow processing to match the cycle time of the memory. Here, low-speed memory is a relative term, and includes IC memory as well as general core memory. Furthermore, in the case of XC memory, past IC memory is used as is,
There is also a demand to speed up only the surrounding circuit system. This is a situation that can naturally occur in the midst of rapid technological progress.

The present invention provides a memory drive circuit that allows even low-speed memory to be accessed by a high-speed peripheral system.

The gist of the present invention is that the output of an address counter and the past output of the address counter are alternately given to the memory as an access address. Hereinafter, the present invention will be explained in detail with reference to drawings.

FIG. 1 shows an embodiment of the memory drive circuit of the present invention, page 3. This is a diagram. Figure 2 shows the time chart.

Address counter 1 counts clock CLKI.

The count output of the address counter 1 is an address, which is input to the selector 3 and buffer register 2. The buffer register 2 latches the counted address (Ao to A?1) Y of the address counter 1 at the timing of the clock CLK2. This latch period is one cycle of the clock CLK2, and for each cycle, the clock CL that starts that cycle is
At the timing of K2, the counted address of address counter 1 at that time is latched. Latch output of buffer register 2 (Y.

~Yn) becomes the selector 30 input.

The selector 3 selects the count address (A
O~An) and the latch output of buffer register 2 (Bo
-Bn) and outputs the selection data. The selector signal SEL performs this selection, and when it is at H level, the latch output (Bo-Bn)
is selected and output, and when it is at L level, the counting address (Ao
-An)y Select and output @The selected output of the selector 3 becomes the access address of the memory 4. memory 4
is a RAM memory, which is read and written in synchronization with the selector signal SEL. When the selector signal SEL is at the H level, the memory 4 performs a read operation, and when the selector signal SEL is at the L level, the memory I 74 performs a write operation in which write data D is written.

The address for the write operation is the latch output of the buffer register 2, and the address for the read operation is the count address. A data latch register 10 latches read data from the memory 4 using a clock CLK2. Write and read commands are omitted.

The above operation will be explained using the time chart of FIG. The clocks CLKI and CLK2 have the same period and different phases. Address counter 1 is clock C
LK1'&count. Therefore, the count value is clock CLKI
The figure shows the argument progression from 1-2 to 3-.... Clock CLK 2 is clock C
It latches the counted address of address counter 1, which has a phase that lags behind LKI and is updated and counted by four clocks CLK1. The latching by CLK2 in the buffer register 2 is the address updated by the previous 5---- page clock CLKI, and after the latching, the counter 1 is updated to a new value (+1) by the new clock CLK2. Therefore, for this new update value, the data in buffer register 2 is the previous count value.

Selector signal SEL input to selector 3 is clock C
A signal synchronized with LK1 and clock CLKI
It has a pulse width Z larger than the pulse width of.

When the selector signal SEL is at H level, the latch output 7 of the buffer register 2 is selected, and when the selector signal SEL is at the H level, the counted address of the address counter 1 is selected. Signal SKL 75
(The output of buffer register 2 at H level is signal SE
This is past data that is delayed by one clock (CLKI) compared to the output of the address counter 1 when L is at the L level.

The numbers in parentheses written on the signal SEL are selector 3.
The selected output value Z is shown. That is, when looking at the input address t from memory 4, 1→0→2→1→3→...
This is an address instruction such as . Among these, the underlined portions 1→2→3→... are addresses for reading, and the remaining six pages 0→1-... are addresses for writing. The memory 4 performs an access operation 7 according to the access contents (write command, read command) at the time, depending on the address output from the selector 3.

According to the embodiments described above, memory driving could be performed while writing and reading were performed alternately and the addresses were being updated. Furthermore, when looking at the reading order, 1 → 2 → 3 →...
・Since reading is performed in the update order, and between readings (for example, between addresses 1 and 2), writing is performed at the previous address (address O).
There is actually more time available for reading. From the memory's point of view, the margin of read time means that the read time of the memory can be slow compared to the speed of the drive circuit (clock CLK2) that drives the memory IJY. That is, according to the present embodiment, a low-speed memory is used as the memory 4 from the viewpoint of actually having the advantage that it is only necessary to use a memory that is slower than the drive circuit. IC memory is a low-speed memory. Of course, core memory, which is commonly referred to as a trap, also falls within this range. Further, when comparing page 7 with the read address and the write address, the read address is the current count address, as shown in FIG. 2, and the write address is the past address. That is, it has the characteristic that the read address is read in real time. In addition, it was possible to provide operations in which reading and writing appear to be performed on locking addresses (meaning all addresses to be updated).

According to the present invention, the relatively slow memory drive 7 is easily made possible by adding a buffer register.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, and FIG. 2 is a time chart. 1...Address counter, 2...Buffer register, 3...Selector, 4...Memory. Patent Applicant: Mr. Hitachi Electronics Engineering Company Representative Patent Attorney: Tadashi Akimoto
-148191CB) Figure 1 Figure 2 Figure 8 - Enfa 2 0 1
2545-

Claims (1)

[Claims] An address counter that counts the first clock and an output t1 of the address counter that has the same period as the first clock? The second clock has a phase that is delayed than the first clock.
a buffer array/zoster that latches with the first clock, and the latch output of the register synchronizes the count address of the address counter with the low level of the selector signal synchronized with the first clock.
a selector that selectively outputs depending on the level and the L level;
Among the selector outputs, latch output 1 of buffer source
A memory drive circuit comprising means for driving a memory as a write address, a counted address of an address counter as a successive address, and a data latch register for latching successive data from the memory using the second clock.