JPS59139195A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide the same storage device with the function of a page and a nibble mode constituting two pairs of a delay circuit and a column address strobe signal (CAS) buffer circuit and constituting the 2nd a CAS buffer circuit by an NAND circuit with an external CAS signal. CONSTITUTION:An output signal CAS2 from the 2nd CAS buffer circuit CB2 is used for controlling address buffers A0-A7, a column decoder DC, data registers DR1-DR4, and an RA7' generating circuits. The secondary address signal RA7' is turned to an ''H'' when RA7 is the ''H'' and CAS2 is turned to the ''H''. Even if the CAS2 is kept at the ''H'', the RA7' is turned to an ''L'' when -CAS1 is turned to the ''H'', and is still kept at the ''L'' even when the -CAS1 is turned to the ''L'' again. Thus, the RA7 and -RA7' are generated synchronously with the CAS2 in the page mode by controlling the RA7' and an optional column address inputted from the external can be selected. In the nibble mode, an optical column address can be selected by the output from a shift register without using the RA7 in the succeeding nibble cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration that enables both page mode and nibble mode on the same semiconductor memory device.

Conventionally, there has been a page mode as one mode of a data read method for a dynamic semiconductor memory device. FIG. 1 shows the timing of reading the external control signal applied to the semiconductor memory device in this mode. in this case,
First, the external row address strobe signal (Ex t
, RAS) becomes active at "L", and using this as a trigger, the internal RAS which is the output of the RAS buffer circuit
Signal (Int, RAS) is “L” from 71 L 11
Using this signal as a trigger, an internal row address is generated, and one word line corresponding to this address is selected.

Next, the external column address strobe signal (Ext
, CAS) enters the active state of "IIL", and using this as a trigger signal, the internal CAS signal (Int, CAS), which is the output of the internal CAS buffer circuit, changes from uLn to IIL.
IH”, using this signal as a trigger, the internal column
An address is generated, one digit line corresponding to this address is selected, and information from one memory cell is read out. Next, Ext, CAS enters the HII inactive state, and the internal CAS signal (Int, CAS), which is the output of the internal CAS buffer circuit, changes from "L" to "H", and this signal causes the column decoder and The data output circuit is reset. Then Ext again.

G-deaf becomes "'L", a different column address is taken in, the digit line corresponding to that address is selected, and data is read out. In this case, since the row address remains the same, page mode switches the memory cells connected to one word line selected by the row address, and the digit line by changing the column address. , it can be called a sequential read mode.

On the other hand, recently, a new data reading method called nibble mode has been proposed and is about to be put into practical use. An example of this literature is the 1981 IEEE.

International 5solid -5tat
e C1rcuits Conference Dig
est of Technical Papers
-84, by S. S. 5he--ffield et al.

The timing diagram of external input signals in this mode is shown in the second diagram.
As shown in the figure. Also, 64 bit dynamic RAM
An example of this construction method is shown in FIG. In this case, first, Ext and RAS become “'L”, and this triggers the internal RAS buffer circuit to operate, and its output Int,
RAS goes from “L” to II H11, which triggers the address buffer circuit (Ni7), and A
, ) ~A, (RA, /'-/RA, ) operates, the row address signal is taken into the semiconductor memory device, and one of the 128 word lines (WLO to WL1'
27) is decoded and selected by the row decoder (RD) by the RAoNRA6. Next, Ext and CAS become "L L 1", and using this as a trigger, the internal CAS buffer circuit operates, and its output Int and CAS become "L".
" to "H'", and using this signal as a trigger, the address buffer circuit (A).

Ni7) works. Of these, AONi2 (CAON
CA6) is input to the column decoder (CD) and 61
Four of the two digit lines are selected,
be done. Therefore, the information of the memory cell (MC) appearing on these four digit lines is transferred to the four pairs of Ilo lines (
Ilo, ~l104) to the data register (D
R.

~DR4). Next, row address A
7 (RA7) and column address Ay (CA7) are data select shift registers (DS, ~DS4).
), one of the four switches (SWI to 5W4) is selected and made conductive, and the contents of the data register are output through the output buffer circuit (OB).

At this time, as shown in Figure 2, Ext and RAS are set to “L”.
”, Ext and CAS are once set to “HII” and then set to “L” again, the shift register operates, the selected switch becomes non-conductive, and the next switch becomes conductive. - As an example, first the SW is set by an external address signal.
If l is selected and conductive, the shift register (DS1) moves by one, SW becomes non-conductive, and SW2 becomes conductive.

In this way, nibble mode sets Ext, RAS to “[
, while keeping TI, set Ext and CAS to “H” → “L” →
When changing from "H'" to "L", the shift register (DSINDS4) operates regardless of the external address, and the data stored in the data registers (DR1 to DR4) are sequentially read out. In this way, unlike the page mode, in the nibble mode, data is read out continuously regardless of the column address, so the internal CAS buffer circuit and address buffer circuit (AO to A7)
Data can be read out at high speed without the need to operate. However, there is a drawback that only 4 bits of data consecutive to the bits selected in advance by the external address can be read.

As mentioned above, although page mode and nibble mode have completely different operations within a semiconductor memory device,
As shown in Figures 1 and 2, Ext, RAS and Ex
Since the timing relationship between t and shiB is exactly the same, conventional semiconductor memory devices cannot distinguish between the two modes, and only one of the modes is possible.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the period of LHII of Ext and CAS is shorter than an arbitrary setting value while Ext and RX'S are in the LII period. If the semiconductor memory device in which the next Ext, CAS is "L" is in the active state, it enters the nibble mode, and if the period in which Ext, CAS is "H" is longer than the arbitrary setting value, the next Ext, CAS is "11". The page mode is set during the L II period, and Ext and CAS are “H”.
The present invention relates to a circuit configuration of a semiconductor memory device in which the next cycle mode can be selected depending on the length of IT time.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of this semiconductor memory device.

The difference from the conventional one is that there are two CAS buffer circuits (
CI3+, CB2) and a generation circuit for a secondary row address RA7' corresponding to a delay circuit (DC) RA7. First CAS buffer circuit (CBl
) has exactly the same circuit configuration as a conventional CAS buffer circuit capable of page mode. FIG. 5 shows an example circuit diagram. In the figure, (1) to (5) are N-channel MO5)
It is a transistor (hereinafter referred to as MO5T).

(6) is the bootstrap capacitance, (7) is the power supply wiring, (
8) is the grounding end. (9) is an amplifier, and 00 is an inverter. Further, in this circuit diagram, circuits not related to the explanation of the present invention are omitted. On the other hand, its output CAS1C
The AS1 signal is used to control the shift registers (DSI to DS) and the output buffer circuit. second CA
A circuit example of the S buffer circuit (CI32) is shown in FIG.

In the figure, (11) to (1161!), @ are N-channel Mos transistors (hereinafter referred to as MO5T), (I
I is a bootstrap capacitance, (17) is a power supply wiring, (to) is a ground terminal, 01 is an amplifier, and 1 is an inverter. The first stage of this CAS buffer circuit is constituted by a NAND gate of Ext, Q/N and the output (CAS D) of the delay circuit (DC), which is a feature of the present invention. The output signal of CB2 (CAS2-self is the address buffer (Ao)
~A7).

Column decoder (CD), data register (DR1~
It is used to control the DR4)# and RA7' generation circuits.

The secondary address signal RA7' is CA when RA is 6 "H".
When S2 becomes “H11”, it becomes “HII” and CAS2
Even if G remains at II H11, if G becomes "HII" it becomes "L" and even if CAS becomes "L" again, L II
It is something that maintains.

By controlling RA7' in this way, in page mode, RA7 + Wataru7' (and CA
71-Ay) is generated, and any column address input from the outside can be selected. In addition, in nibble mode, after RA7*Ca2 is generated in synchronization with CAS, even if CAS2 remains “H”, CAS remains “H”.
When it becomes "H", both RA7 and bean 7 become "L", and in the following nibble cycle, selection can be made by the output of the shift register regardless of RA.

FIG. 7 shows an example of a circuit constructed from the RA7/generating circuit MOS transistors described above.

Next, the operations of these circuits will be explained using their output waveforms. Figure 8 shows Ext, RAS, Ext, zG
and CB 1 * D C * CB2 + RB + R
It shows the relationship with the output waveform of A7'*RA7'. In the figure, arrows indicate the flow of signals that serve as triggers. That is, the output RAS of the RAS buffer circuit (RB) is an inverted signal generated in synchronization with Ext and RAS. Therefore, when RAS becomes "Hll", the node B in FIG. 6 is charged to "Hll". Therefore, the gates of MOS T(1) and (4) become "HII level", and both MO8Ts are turned on.However, at this time, if Ext and CAS are "H", MO8T(2)
and (5) are also turned on, and if the ratio of MO8T (1) and (2) and MO5T (4) and (5) is maintained sufficiently, nodes A and C will be at "L" level. However, Ext.
When CAS becomes L II, MO5T (2) and (5) are turned off, and node prisoner and (C) become “HII level” and C
ASl is also “IIH”. That is, CAS is Ext, C
This becomes an inverted signal synchronized with AS. Therefore, CAS1
Generated using a signal as a trigger.

The GB1 signal is also generated in synchronization with Ext and CAS.

CASI, CASI (No. iii) Since it controls the shift registers (Ds1 to Ds4) and the output buffer circuit, this Rano circuit repeats operation and reset in synchronization with the Ext and CAS signals.

Next, the fall of the output signal CAS D of the delay circuit (D'C) is configured so that it becomes "l L l" without much delay when Ext and CAS become "L" as a trigger. On the other hand, at the start, 1 ml is “1L□′”
IIH” with a delay time (1)
On the other hand, the second CAS
The first stage of the buffer circuit (CBz) is Ext as shown in FIG.

It is composed of a NAND gate of CAS and CAS D, and its output CAS 2 is
” is determined by turning off one of the transistors of MO8T Q3 & 61!υ. In other words, whichever of CAS D, Ex t, and δ West- becomes “L” At this point, CAS becomes H”. By the way, the “L” of CAS D is CA
The trigger is when Sl becomes “HII”, and CA
The reason why S becomes 'H' is Ext.

” becomes “L”, so it is always E.
xt, Chiang quickly becomes <PAL”.
The rising edge of 2 is always determined using Ext and CAS as triggers. On the other hand, when CAS2 becomes “L”, MO
When both 8Tσ and 121) are on, that is, Ext, C
This is when AS and CAS D become "H". Therefore, E
xt, when the CAS time is 1 (1+ < 1), the C rock remains at "L", so CAS2 remains at "HII". Moreover, when the time of Ext and CAS is t2 (L2>t), and [D becomes "'H" after time t has passed since CASI became "H". Then, CAS2 becomes "'L°". Also, this CA
CAS2 is generated using the S2 signal as a trigger.

Therefore, CAS2 and CAS are Ext, and CAS is I
If the time of I HII is shorter than t, there is no change, and t
If it is longer, it will change. The CAS2 signal is used to generate column address RA7' and data register (DRI).
~DR4), and CAS2 controls the column decoder (CD) and data register (DRINDR4).
Used for resetting. Therefore, Ext, CAS “
If the time of L″″ is shorter than t, the data register (D
Rl ”□ DR4) and column decoder (CD) maintain their previous states, only CASl occurs and shift
Registers (DSI to DS4) and output buffer circuits (O
B) works, but at this time RA? ' * Since both RA7' signals are kept "L", the next Ext and CAS will be I
The period in which "IL" is in the active state is in nibble mode.

On the other hand, if the "H" time of Ext and SiB is longer than t, the data registers (DRI to D
R4), column decoder (CD), address buffer circuit, etc. are all reset, and Rk; *RA
'l is generated in synchronization with CAS2, allowing page mode in the next cycle.

By using the RA7' generation circuit according to the present invention, page mode and nibble mode can be compatible on the same chip in a system in which the first bit of the four nibble bits is determined by the two bits of the row address and column address. becomes possible.

Note that the above embodiments only show circuits as examples, and other circuit configurations that configure a NAND circuit of the output of the delay circuit and the external CAS signal at the first stage will have the same effect. Needless to say. Also,
Although the above embodiment has been described using an N-channel MO8 transistor, the same effect can be achieved by using a P-channel type or CMO8 structure, or even a bipolar transistor.

As described above, according to the present invention, two delay circuits and two CAS buffer circuits are configured, and the second CAS buffer circuit is configured as Ext, ? Th Summer and Ext, “HIT” from “L” of the stone mill
N
Since it is constructed using an AND circuit, it is possible to provide two functions, page mode and nibble mode, in the same semiconductor memory device.

[Brief explanation of drawings]

Figure 1 shows external RAS and CA in page mode.
FIG. 2 is a timing chart of external RAS and CAS signals in nibble mode, FIG. 8 is a block diagram of a semiconductor memory device capable of nibble mode, and FIG. 4 is a page and A block diagram of a semiconductor memory device capable of nibble mode, FIG. 5 is a conventional CAS buffer circuit diagram, and FIG. 6 is a CAS buffer circuit diagram of the present invention.
Buffer circuit diagram, FIG. 7 is a diagram showing a secondary row address signal RA7' generation circuit which is a feature of the present invention, and FIG. 8 is a timing chart diagram showing internal RAS and CAS signals in the present invention. (CBI) (CB2)...CAS buffer circuit, (
DC)...Delay circuit, (t) ~ (5), an ~0
-6, ezL @-MO8T, (6), Q4-
...Bootstrap capacitance, (7), ση...power supply wiring, (8), (to)...ground terminal, (9)ll field...
Amplifier, QO, (a)...Inverter Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 5, Figure 6, Figure 7 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Patent application No. 5 S-+S+SO 1 No. 2, title of the invention, semiconductor storage device 3, amends. To Representative Hitoshi Katayama, Department 4, Agent 5, Detailed Description of the Invention in the Specification Subject to Amendment, Column 6, Contents of Amendment (1) The specification is amended as follows. (2)

Claims (1)

[Claims] External column address strobe signal (Ext, CAS)
A delay circuit that changes from "L" to "H" with a delay of a certain set value when the transition from "L" to "H", and two C
AS buffer circuit, the first CAS buffer circuit operates in synchronization with the Ext and CAS signals, and the second CAS buffer circuit operates in synchronization with the Ext and CAS signals.
A semiconductor memory device characterized in that the first stage of the AS buffer circuit is constituted by a NAND gate that receives the Ext and CAS signals and the output signal of the delay circuit, wherein at least one row address signal is input to an external row address. Strobe signal (Ext, RAS) is “L”
generates a secondary row address corresponding to the row address held in synchronization with the output signal (CAS 2 ) of the holding means and the second CAS buffer circuit for a certain period; Buffer circuit output signal (CA
A semiconductor memory device characterized by having means for setting all of the secondary row addresses to "L" in SI).