JPS59135694A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide two functions of page mode and nibble mode by a semiconductor storage device by constituting the 2nd CAS buffer circuit with an NAND circuit for an external column address storobe signal (Ext.CAS) and a signal going to H with a delay time when the Ext.CAS goes from L to H. CONSTITUTION:An output RAS of an RAS buffer circuit is an inverting signal generated in synchronizing with the Ext.RAS. Thus, a node B is brought into H when the RAS goes to H. Thus, a gate of MOS transistors (TRs) 1, 4 goes to H level and both the MOS TRs are turned on. On the other hand, when the Ext.CAS is at H in this case, MOS TRs 2, 5 are turned on and the nodes A and C go to L level when the ratio between the MOS TRs 1, 2 and the MOS TRs 4, 5 is taken sufficiently. When the Ext.CAS goes to L, the MOS TRs 2, 5 are turned off, the nodes A, C go to H level and the CAS1 goes to H.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides for
The present invention relates to a circuit configuration that enables both nibble mode and nibble mode.

[Prior art]

Conventionally, there has been a page mode as one mode for successively outputting data in a dynamic semiconductor memory device. FIG. 1 shows the timing of reading external control signals applied to the semiconductor memory device in this mode. In this case, first, the external row address strobe signal (Ext
-RAS) enters the active state of "L". Using this as a trigger, the internal RAS signal (Int-RAS), which is the output of the RAS buffer circuit, changes from "L" to H. Using this signal as a trigger, An internal row address is generated, and t: one word line is selected corresponding to this address.

Next, external column address strobe (No. 8 (Ex
lCAS) becomes active at L'', and using this n as a trigger, the internal CAS signal (Int-CAS), which is the output of the internal CAS buffer circuit, changes from 1L'' to H''. Using this signal as a trigger, the internal column address is generated and one digit line corresponding to this address is selected.
Information of one memory cell is read. Then ExlCA
S becomes inactive state of 6H", and the internal CAS signal (Int-CAS), which is the output of the internal CAS buffer circuit, becomes 1.
From L" to 1H", this signal resets the column data and data output circuit. Then, once again, ExtCAS is set to 6L'', a different column address is the input port, the t-order line corresponding to that address is selected, and the data is read out.In this case, the row address remain the same, so in page mode, the memory cells connected to one word line selected by the row address are read out sequentially by changing the column address to switch the digit line. It can be called a mode.

On the other hand, recently, a new data reading method called nibble mode has been proposed and is about to be put into practical use. An example of this is the 1981 IEEE International 5
o11d-5tate C1rcuits Confe
renae's]) igest of Technic-
al Papers P, 84, S, S, 5hef
fie': Introduced by i et al.

The timing diagram of external input signals in this mode is shown in the second diagram.
As shown in the figure. Also, 64 bit dynamic RAM
An example of this construction method is shown in @8 factors.

In this case, first, ExiRAS becomes "L", the internal RAS buffer circuit operates using this as a trigger, and its output In1RAS changes from "L" to H, and this is the address buffer circuit (Ao to A7). ) trigger and A7 operates, the row address signal is taken into the semiconductor memory device, and one of the 256 word lines (WL
O-WL255) is selected by the row decoder (RD). Next, Ext-cAs changes to "L", the internal CAS buffer circuit operates using this as a trigger, and its output IntCAS changes from "L" to "H", and using this signal as a trigger, the address buffer circuit (Ao =A7)
works. Among them, Ao to A5 are column decoders (
(2) Four digit lines are selected from among the 256 digit lines input in n2.

Therefore, the information of the memory cell (MC) appearing on these four digit lines is transferred to the four pairs of I10 lines (I101 to I101).
1104) and the data registers (DRI to DR
4). Next, the remaining column address (A
a+Ay) is the data select shift register (
DSI to DS4), and four switches (SWI
~SW4) is selected and made conductive, so that the contents of the data register are transferred to the output buffer circuit (OB
) and output.

At this time, as shown in Figure 2, Ext-RAs is set to "L".
”, press Ext to set the rock to “H”, and then again.
When set to "L", the shift register operates, the selected switch becomes non-conducting, and the next switch becomes conductive.-
As an example, if SWI is selected by the column address (A6.AV) and is conductive, the shift register (DSI) moves by one, SWI becomes non-conductive, and SW2 becomes conductive.

In this way, in the nibble mode, EXt-RAS is kept at L" and Ext-CAS is set to fi H* → II L".
→"H"→1L", the shift registers (DSI to DS4) operate regardless of the external address, and the data stored in the data registers (DRI to DR4) are sequentially read out. In this way, the nibble mode differs from the page mode in that data is read out regardless of the column address, so there is no need to operate the internal CAS buffer circuit and address buffer circuit (Ao-At), and the data can be read out at high speed. Data can be read out. However, there is a drawback that only 4 bits of data selected in advance by the column address (Ao to As) can be read out.

As described above, although page mode and nibble mode operate completely differently within a semiconductor memory device,
As shown in Figure 2, Ext・RAS and Ext・-
Since the timing relationship between the two modes is exactly the same, conventional semiconductor memory devices cannot distinguish between the two modes, and only one of the modes is possible.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. During the period when ExlRAS is L'',
If the period of "H" of the Ext-group is shorter than the arbitrary setting value, the next Ext-CAS is "L" and the semiconductor memory device is in the nibble mode during the active state period.
” period is longer than the arbitrary setting value, the next Ext-
The page mode is set during the period when cAs is L'', and E
The present invention provides a circuit configuration of a semiconductor memory device in which the next cycle mode can be selected depending on the length of 1H'' of xt-CAS.

[Embodiments of the invention]

Hereinafter, one embodiment of F1 will be explained using the light.

FIG. 4 is a block diagram of this semiconductor memory device. The difference from the conventional one is that two CAS buffer circuits (CBI
) (CB2) and a delay circuit (CD). The first CAS buffer time W1 (CBI) is
It has exactly the same circuit configuration as a conventional CAS buffer circuit capable of page mode. FIG. 5 shows an example circuit diagram. In the figure, (1) to (5) are N-channel MOS transistors. (6) is the bootstrap capacity, (7)
is the power supply wiring, and (8) is the ground terminal. (9) is a amplifier,
QO is an inverter. Further, in this circuit diagram, circuits not related to the explanation of the present invention are omitted.

- 10,000, its output CAS1, CAS1 signal is used to control the shift register (DSI-DS4) and output buffer circuit. Second CAS buffer round II @(C
A circuit example of B2) is shown in FIG. In the figure, 0]) to (1,
112υ, @ is N-channel MOS +- transistor,
qQ is the footstrap capacitance, αη is the power supply wiring, α is the ground terminal, Ol is the amplifier, and (a) is the inverter. The first stage of this CAS buffer circuit is constituted by a NAND gate of Ext·-δwest- and the output (CASD) of the delay circuit (DC), and this gate is a feature of the present invention. CB2
The output signal (CAS2.2) is used to control the address buffer (Ao to A?), column decoder (CD), and data register (DRI to DR4).

Next, the operation of these circuits will be explained using their output waveforms. Figure 7 shows Ext-I Rock, Ext-J Deaf and CBI.
, DC, CB2. It shows the relationship with the RB output waveform.

In the figure, arrows indicate flow ports for signals that serve as triggers. That is, the output RAS of the RAS buffer circuit (RB) is Ex
This is an inverted signal generated in synchronization with lRAS.

Therefore, when RAS becomes H, node B in FIG. 5 is charged to H. Therefore, the gates of MOS transistors (1) and (4) are not at H level, and both MOS transistors are Turn on.

However, at this time, ExtCAS is “H” and M
OS l-transistors (2) and (5) are also on,
If the ratio of MOS transistors (1) and (2) and MOS transistors (4) and (5) is set sufficiently, nodes A and C become "L" level.However, EX t-C
When AS becomes 1L", MOS l-transistors (2) and (5) are turned off, nodes (5) and (C) become H" level, and CASI also becomes "H". That is, CASI is E
This is an inverted signal synchronized with xt.

Therefore, τ generated using the CASI signal as a trigger
The Ext.31 signal is also generated in synchronization with noon.

CASI, 6 rock 1 signal is shift register (DSI-
O84) and the output buffer circuit, these circuits repeat operation and reset in synchronization with the lli:xtCAS signal.

Next, the falling edge of the output signal ASD of the delay circuit (DC) is configured to become "L" without any delay, triggered by EXt-CAS becoming "L".

On the other hand, the rising p is set so that CASI becomes 'H' with a certain delay time (tl) from 6L'' to 1H''.On the other hand, the second CAS buffer circuit (CB2
) is composed of Ext-CAS and C as shown in Figure 6.
It is composed of a NAND gate with ASD, and when the output CAS2 rises from L'' to @H'', MO
It is determined by turning off one of the S transistors Q2+ and ■η. That is, CA
When SD or Ext-CAS, whichever is earlier, becomes L", CAS 1 becomes H".

By the way, CASD becomes “L” when CASI is @
The trigger is when EX t-CAS becomes "H", and the trigger for CASI to become "H" is when EX t-CAS becomes "L", so Ex t-CAS is always early ("L").
”. Therefore, when CAS2 rises, E is always
It is determined using xt-CAS as a trigger. -10,000, CAS
2 becomes L” because MOS transistor 02 and
This is when both ExlCAS and CASD are turned on, that is, when ExlCAS and CASD become H". Therefore, the time of ExlCAS is t
When 1 (tl<t), CASD remains @L'', so CAS 2 remains H'''. Also, EX
When the time of t-CAS is t2 (t2>t), CA
SD becomes "H" after time t has passed since CAS 1 becomes @H. Therefore, at this point, CAS 2 becomes "L". Also, using this CAS 2 number as a trigger, 6 prisoners 2 is generated.

Therefore, CAS 2 and CAS 2 do not change if the time when Ext- and deafness is “H” is shorter than t,
If it is longer than t, it will change. CAS2 signal is column
Address generation and data registers (DRI to DR)
4), and CAS2 controls the activation of column decoder (
CD) is used to reset the data registers (DRI to DR4). Therefore, if the time of ExlCAS H" is shorter than t, the data register (DRI~D
R4), and the column decoder (CD) maintain their previous states, only CAS 1 is generated, and the shift register (DS 1 = DS 4) and output buffer circuit (OB
) operates, the next active period in which the Ext- phase is "L" is in the nibble mode.

10,000, if the time of ExlCAS H" is longer than t,
In addition to shift registers (DSl-DS4) and output buffer circuits (OB), data registers (DRI-DR4)
).

The column decoder (CD), address buffer, etc. are all reset to enable page mode in the first cycle.

Note that in the above embodiment, only an example circuit is shown, and the same effect can be obtained in other circuit configurations of 1L, where the output of the delay circuit in the first stage constitutes a NAND circuit with the external CAS signal. It goes without saying that you should have one. Further, in the above embodiment, an N-channel MOS transistor was used, but a P-channel MOS transistor or a Cl
A similar effect can be obtained by using an O2 structure or even a bipolar transistor.

〔Effect of the invention〕

As described above, according to the present invention, two delay circuits and two CAS buffer circuits are configured, and the second CAS buffer circuit is configured at the time of transition from 1L" to 1" for deafness. NA with the signal that becomes “H” with delay time
By configuring multiple NDl paths, the same semiconductor memory device can have two functions, a page mode and a nibble mode.

[Brief explanation of the drawing]

FIG. 1 shows the external RAS in page mode. CAS signal timing chart, Figure 2 is a timing chart of external phase signals in nibble mode, Figure 8 is a block diagram of a semiconductor memory device capable of nibble mode, and Figure 4 is the present invention. Block configuration diagram of a semiconductor memory device capable of page and nibble modes in 5th
FIG. 6 is a conventional CAS buffer circuit diagram, FIG. 6 is a CAS buffer circuit diagram used in the present invention, and FIG. 7 is a timing chart showing internal RAS and CAS signals in the present invention. (DC)...Delay circuit, (CBI) (CB2)...
・CAS buffer circuit, 0υ~Qi9, el! ])
, IE...MOS transistor, OQ...bootstrap capacitor, θ'i)...-source wiring, θ mark...
- Grounding end, 09... Amplifier, Hanging... Inverter Note that the same reference numerals in the drawings indicate the same or equivalent parts. Agent Makoto Kuzuno - Procedural amendment (indication 20 Name of invention semiconductor storage device 3, Name of person making the amendment (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 6, Invention of the specification subject to amendment Item 6 of the Detailed Explanation, Contents of Amendment (1) The specification is amended as follows.

Claims (1)

[Claims] External column address strobe signal (Ext/CA
A delay circuit that changes from L'' to H'' with a delay of a certain set value when the S signal) transitions from “L” to H”;
a first CAS buffer circuit that operates -h in synchronization with the A semiconductor memory device comprising: