JPS6352398A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify a circuit by decoding initial address for random input/ output and serial input/output by a common column decoder. CONSTITUTION:Random output or random input is executed according to the low level of an output enable signal OE (DT/OE) or a write enable signal WE at the time of low level of a signal RAS. In such a case, an address signal taken in an address register RAR is decoded by a column address decoder C-DCR, and the selecting action of a column switching circuit CSW is performed. On the other hand, transfer from a memory array M-ARY to a latching circuit PDFF or DFF or transfer from the latching circuit PDFF or DFF to the memory array M-ARY is executed according to the high or low level of the write enable signal WE at the time of the trailing of the signal RAS. Thereby, a column decoder can be used in common for random input/output and serial input/output.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in a dual port memory that has a serial input/output function and a random input/output function for image processing and the like.

[Conventional technology]

As an effective image processing memory for displaying characters and figures on the screen of a CRT (cathode ray tube), for example, Nikkei McGraw-Hill, February 11, 1985, "Nikkei Electronics", pages 219 to 229; 8
“Nikkei Electronics 1, pp. 211-24, dated May 12th.
A dual-port memory described in No. 0 is known.

[Problem that the invention seeks to solve]

The former dual port memory transfers a signal from a memory array to a shift register in parallel and outputs it serially, or serially inputs a signal to a shift register and writes it in parallel to the memory array.

Therefore, in serial input/output, the start address is fixed, which limits its use.

On the other hand, the latter dual-port memory requires dedicated decoder circuits for the random access operation of the memory array and for the serial output operation, so its circuit configuration is complicated. In addition, serial output operation uses a dynamic latch circuit that takes in data signals from the memory array in parallel and outputs them serially, which also functions as an amplifier circuit, so it only has a serial output function and does not have a serial input function. .

Further, as semiconductor technology progresses, the actual number of memory cells coupled to one word line can be increased relative to the number of pixels in the horizontal direction of a CRT screen.

Therefore, as a memory for image processing, it is necessary to input and output data in an arbitrary area among data consisting of a plurality of bits corresponding to one word line of the memory array. However, with the above-mentioned conventional method, it is not possible to input/output data in the above-mentioned arbitrary area at high speed.

An object of the present invention is to provide a semiconductor memory device with simplified circuitry and improved functionality.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, for serial input/output, a first latch circuit transmits and receives signals to and from the data line of the memory array in parallel according to a first transfer timing signal, and a latch circuit that transmits and receives signals to and from the data line of the memory array according to a second transfer timing signal. a second latch circuit that transmits and receives signals in parallel with the first latch circuit; and a serial input/output provided between the first or second latch circuit and a second common data line. , a start address register to which a start address signal is supplied, and a signal formed by reading the address signal supplied to the start address register by the above-mentioned column decoder and supplied as an initial value, and the shift operation is performed. a shift register which forms a selection signal for the switch circuit for serial input/output, and a first register to which the first and second address signals are respectively supplied.
and a second end address register, an address counter whose initial value is set by the signal of the first end address register, and the start address register, and which counts serial input/output operations by the shift register; the output signal and the first or second
and a comparison circuit that receives the output signal of the end address register, and when the serial data input/output operation is started from the address specified by the start address register, the output signal of the first or second end address already written is provided. Performing a serial input/output operation up to the address specified by the register, and in parallel with this serial input/output operation, fetching an end address signal for the next operation cycle into the second or first end address register, In the next (7) It operation cycle, the memory array signal to be input/output is taken into the first or second latch circuit.

[For production]

According to the above-mentioned means, initial addresses for random input/output and serial output can be decoded using a common column decoder, and a certain range of data from the word lines of the memory array can be designated and serialized. Can input and output.

〔Example〕

In the first view, a block diagram of an embodiment of the present invention is shown. Each circuit block in the same figure is manufactured using a known semiconductor integrated circuit manufacturing technology, in particular j), 11, but not limited to,
It is formed on a single semiconductor substrate such as single crystal silicon. Each major circuit block in the figure is drawn according to the actual geometric arrangement on one chip.

Although the semiconductor memory device of this example is not particularly limited,
The basic configuration is a dynamic RAM memory array that is accessed in units of 1 bit (×1 bit configuration).
As described below, various circuits are added to realize serial input/output functions for image processing operations. For example, when storing a signal consisting of 4 bits of red, blue, green, and luminance for color image processing, the memory array M-ARY, the random input/output circuit I10, and the serial input/output circuit SIO in the same figure are used. There are a total of four sets, each corresponding to each of the above-mentioned signals.

The memory array M-ARY includes dynamic memory cells each consisting of an address selection MO3FET (insulated gate field effect transistor) arranged in a matrix and an information storage capacitor. The address selection MO3FET of the memory cell has its gate coupled to a corresponding word line, and its drain coupled to a data line. The word line and data line are configured by a known two-intersection (folded focus line or digit line) method, and the drain of the address selection MO3FET of the memory cell is connected to the pair of complementary data lines arranged in parallel. Of these, the corresponding data line is coupled to one of the data lines. Although not shown, the complementary data line also includes a precharge circuit,
A sense amplifier and an active restore circuit are each provided.

It should be understood that each of these circuits is included in the memory array M-ARY in the figure. The configuration of such a memory array is similar to that of a known dynamic RAM, so a detailed explanation thereof will be omitted.

The memory array M-ARY complementary data lines are connected on one side to common complementary data lines CD and CD for random input/output, which will be described later, via a column switch circuit C8W.

Although not particularly limited, the complementary data line of the memory array M-ARY is connected to the first data holding latch circuit PD via the parallel transfer gate circuit TFG1.
It is coupled to the input/output terminal of the FF. This latch circuit PDF
The input/output terminal of F is connected to the second parallel transfer gate circuit T.
The second data holding latch circuit DFF is connected via FG2.
is supplied to the input/output terminals of Each input/output terminal of this latch circuit DFF is connected to a serial selection circuit SR&sw consisting of a shift register SR and a serial switch circuit SSW.
A common data line CD' for serial input/output, as will be described later, is provided via the respective switch circuits of o.

CD'.

In this embodiment, in order to enable serial input/output from any bit, the output signal of the final stage of the shift register SR is fed back to the first stage circuit. This causes the shift register SR to perform a ring-shaped shift operation.

The shift register SR has its initial value (logic "1") formed by decoding the start address signal taken into the start address register SAR by the column decoder C-DCR during the serial transfer mode, which will be described later. In other words, in the shift register SR, a selection signal of logic "1" is applied to the bit corresponding to the complementary data line of the memory array designated by the start address signal (column address signal) taken into the start address register SAR. is set. The above shift register S
R receives the shift clock signal φS formed by the timing control circuit TC based on the clock signal supplied from the external terminal CLK, and selects the selection signal (logic "1").
”) shift operation.

The common complementary data lines CD, CD are connected to a random input/output circuit I which consists of an output circuit consisting of a main amplifier and a data output cover sofa, and an input circuit consisting of a data input cover sofa.
10 to a random input/output terminal. The common complementary data lines CD', CD' are coupled to a serial input/output terminal Ds via a serial input/output circuit S10 consisting of an output circuit consisting of a main amplifier and a data output cover sofa, and an input circuit consisting of a data input cover sofa. Ru. Each of the above-mentioned serial input/output circuits is constituted by a Scuti Sok type circuit.

Row address buffer R-ADB receives external address signals AXO to AXn in synchronization with a timing signal (not shown) generated by row address strobe signal RAS
and forms an internal complementary address signal to be transmitted to the row address decoder R-DCR. The row address decoder R-DCR decodes the address signal supplied from the row address buffer R-ADB and selects a predetermined word line (and dummy word line) in synchronization with a word line selection timing signal (not shown). perform an action.

The column address buffer C-ADB receives an external address signal A Y O-A Y n in synchronization with a timing signal (not shown) formed by a column address strobe signal CAS that is supplied with a delay, and randomly outputs the external address signal A Y O-A Y n according to the operating mode signal at that time. It is selectively supplied to the address register RAR for access, the start address register SAR for serial access, and the first end address register EAR1. Therefore, the column address decoder C-DCR selectively selects each of the registers RAR and S via the multiplexer MPX according to the operating mode at that time.
It decodes the address signal supplied from the AR, and also performs a data line selection operation or an initial value setting operation for the shift register SR in synchronization with a data line selection (column switch selection) timing signal (not shown).

The signal of the first end address register EAR1 is:
It is transferred to the second end address register EAR2.

On the other hand, the start address signal taken into the start address register SAR is sent to the address counter C0U.
Provided to NT as an initial value. This address counter circuit COUNT performs a counting operation of the shift clock signal φS of the shift register SR in the serial transfer mode.

As a result, the count value of the counter circuit C0UNT is adjusted according to the input/output data in the serial transfer mode.
Instructing the dress. Therefore, in order to detect that serial input/output up to the specified end address has been performed, the count output signal of the counter circuit C0UNT and the end address signal held in the second end address register F, A R2 are used. is supplied to a comparison circuit (digital comparator) DCMP. Comparison circuit D
CMP is an end signal E when the serial input/output operation up to the above end address is performed, in other words, when the address count output and the end address signal match.
Form ND.

The timing control circuit TC operates upon receiving an address strobe (RAS, CAS1 write enable signal WE, data transfer and output enable signal DT10E, and a clock signal CLK used for serial input/output operations) supplied from external terminals. Identifies the mode and generates various timing signals accordingly.

As mentioned above, the memory array M- shown in FIG.
The circuit blocks placed between them are actually arranged in this geometrical arrangement on one chip. This makes it possible to perform random input/output and serial input/output, as will be described in detail later, and further enhances its functionality and improves the degree of integration.

FIG. 2 shows a circuit diagram of a specific embodiment of each of the random input/output and serial input/output circuits.

In the figure, a P-channel MO3FET is distinguished from an N-channel MO3FET by adding an arrow to its channel portion.

Complementary data lines DO and DO in the memory array M-ARY (not shown) are connected to a switch MO3FETQ1 that constitutes a column switch circuit ucsw for random input/output.
6 and Q17 to common complementary data lines CD and CD for random input/output. These switches MO3F
Column decoder C is connected to the gates of ETQI 6 and Q17.
-DCR selection output signal yo is supplied.

Complementary data 4iD in the memory array M-ARY
On the other hand, O and Do are switches MOS that form the parallel transfer gate circuit TFG1 of the first unit.
It is coupled to the input/output node of the first unit data latch circuit UPDFF via FETQ5 and Q6. The configuration of this unit latch circuit UPDFF is explained in the second section described later.
The configuration is similar to that of the latch circuit U D F F . A transfer timing signal φtfl is supplied to the gates of the switches MOS FETs Q5 and Q6 along with other similar MOS FETs, and the MO3FETs Q5. Q6
is controlled by the switch.

A pair of input/output nodes of the latch circuit UPDF of the first unit are connected to the parallel transfer gate circuit TF of the second unit.
Switch MO3FETQ3 configuring G2. It is coupled to the input/output node of the second unit data latch circuit UDFF via Q4. The above switch MOS FET
The gates of Q3 and Q4 are connected to other similar MOS F E
A transfer timing signal φtf2 is supplied together with T,
MO3FETQ3. Q4 is thereby switch-controlled. The latch circuit tJDFF of the second unit is, although not particularly limited, an N-channel MO3FETQ? , Q9 and P-channel MO3FET Q8. It is constructed by cross-connecting the inputs and outputs of two CMOS inverter circuits consisting of QIO.

A pair of input/output nodes D of the above unit latch circuit UDFF
On the other hand, O' and DO' are switch MOS F constituting a unit switch circuit SW for serial input/output.
It is connected to common data lines CD' and CD' for serial input/output via ETQ 1 and Q 2 . The commonly connected gates of these switches MOS FET Q1 and Q2 are connected to the output signal SLO of the unit circuit USR (unit circuit corresponding to complementary data 'WDO1DO) constituting the shift register SR. Supplied as a signal.

The shift register USR of the above unit has a half-vinit circuit in the previous stage that is composed of two C
(P-channel type transmission game that transmits MOS inverter circuits INI and N2 and their output signals to the subsequent half-focus circuit)
Consists of MO3FETQI 2. Note that in the feedback inverter circuit N2, the conductance of the MOSFET that constitutes it is made small. As a result, the input signal of the inverter circuit N1 is an N-channel type transmission gate.
) The level is set according to the signal transferred from the previous stage via MO3FETQil. In other words, the output signal of the inverter circuit N1 is inverted by the signal supplied via the MO3FET Q11. Toki P
Channel type transmission gate Mo SF ETQ 12
The subsequent half-bit circuit which receives the signal transferred by the circuit is also composed of CMOS inverter circuits N3 and N4 similar to those described above, and an N-channel type transmission gate MO3FET QI3 which transmits the output signal from the CMOS inverter circuits to the next stage circuit. The shift clock signal φS is commonly supplied to the gates of the MO3FETs QII to Ql3 for signal transfer. The signal at the input terminal of the latter half-bit circuit is the selection signal SL.
0 to the gates of the MO3FETs QI and Q2. Note that the inverter circuits N5 and N6 are
This constitutes the next stage shift register. The final stage output of the shift register is the transmission gate MO3FETQ13.
The output of the impark circuit that constitutes the latch circuit is MO3FE without passing through the transmission gate MO3FET corresponding to
Returned to TQI 1. Considering the wiring path length for this feedback, the output of the final stage is amplified by the drive circuit and fed back.

The unit circuit USR constituting the shift register SR is supplied with the output signal YO of the column decoder C-DCR via a switch MO3FETQ15 for initial value setting. That is, a signal having the opposite phase of the signal YO supplied to the random input/output switch circuit ucsw corresponding to the unit circuit USH is supplied. Above switch MO3FF, TQ
15, along with other similar switches MO3FETQI 4, are switch-controlled by a preset timing signal φset. For example, the output signal YO formed by the column decoder C-DCR is at a low level (logic “0”).
If it is the selection signal of
imported in sync with.

Other unit circuits have high-level (logical "
A non-selection signal of "1") is supplied via the switch MO3FETQ14 etc.The column decoder C-DCR converts the high level to logic "1".

When the shift register SR is configured with a NAND gate circuit, its output signal (low level) is directly supplied as the initial value of the shift register SR. Therefore, when a decoder circuit with a Nant gate configuration as described above is used, MO3FETQI 6. which constitutes the column switch circuit for random input/output is used. The output signal of the column decoder CDCR is inverted and supplied to the gate of Ql 7 according to the data selection timing signal. In addition, when one of the switch circuits u cs W and SSW is composed of only an N-channel LumioSFET and the other is composed of only a P-channel MOS FET, the in-phase output from the column decoder C-DCR can be used as the selection signal.

The operation of this unit of soft register USR is as follows. When the clock signal φS is at a high level, the N-channel type transmission gates MO3FETQll and Ql3 are turned on, and a half-bit shift operation is performed. For example, a low level selection signal is transferred from the previous stage circuit to the input terminal of the inverter circuit N1 via the MO3FET QI1.

At the same time, the output signal (high level) of the inverter circuit N3 is transferred to the next stage circuit via the MO3FET QI3.

Next, when the clock signal φS changes to low level,
Since N-channel MO3FETQI1 and Ql3 are turned off and P-channel MOSFETQI2 is turned on, the output signal of inverter circuit N1 (high level)
is transmitted to the input side of the next half-bit circuit. As a result, the switches MOS FET Q1 and Q2 are turned on, and for the common data yACD', CD-, the input/output node DO held in the unit latch circuit UDFF is turned on.
', DO'' signals are transferred and output to the external terminal Ds via a main amplifier and an output circuit (not shown).

Next, when the clock signal φS is set to high level again,
A high-level non-selection signal is transferred from the previous stage circuit to the input of the inverter circuit N1, and at the same time, the inverter circuit N3
A low level selection signal is transferred from the output of the circuit to the next stage circuit. Then, when the clock signal φS is set to a low level, a low level is transmitted to the input of the inverter circuit N3, so that the switches MO3FETQI and Q2 are turned off, and the switch MOS of the switch circuit SW corresponding to the next stage circuit is turned off. FET is turned on, and the holding signal of the previous latch circuit UDFF corresponding to the next stage circuit is transferred to the common data lines CD' and CD'. Thereafter, the serial output operation is performed by repeating similar operations. On the other hand, the operation of the shift register SR similar to that described above enables serial input operation. Input data synchronized with the clock signal φS is continuously supplied from the serial input/output terminal Ds to the common data lines CD' and CD' via the serial input/output circuit. In synchronization with the clock signal φS, the common data line is sequentially connected to the latch circuit UDFF of the unit selected by the output of the shift register,
Retain input data. Note that when the above initial value is set, a high level selection signal SLO is generated in synchronization with the low level of the clock signal φs.

Next, m operations of the semiconductor memory device of this embodiment will be simply explained according to the timing chart shown in FIG. In the semi-quadramid storage device of this embodiment, random input/output and serial input/output are possible, and serial input/output and random input/output can be performed in parallel. If the data transfer and output enable signal DT10E is at a high level when the row address strobe signal RAS, which is a substantial chip selection signal, falls from a high level to a low level, the random input/output mode is set. That is, random output or random input is performed according to the output enable signal OE (D T /' OE ) when the signal RAS is at a low level or the write enable signal WE is at a low level. At this time, the random output or random input is performed in synchronization with the signal CAS. The column address signal is the address register RAR.
be taken in.

The address (
The message is decoded by the column address decoder C-DCR, and the column switch circuit csW performs a selection operation.

On the other hand, before the signal RAS falls, the signal rises.

If T/○E is at a low level, 6° input/output to the rung is not performed, and a transfer mode is set in which data is transferred between the memory array M-ARY and the latch circuit PDFF or DFF. That is, depending on the high level or low level of the write enable signals W and E when the signal RAS falls, the transfer from the memory array M-ARY to the latch circuit PDFF or DFF or the latch circuit PDF
Data transfer from F or DFF to memory array MARY is performed. In this embodiment, a start address and an end address for serial output or serial input are specified. Although not particularly limited, a dummy cycle is executed to specify the end address. In this dummy cycle, column address strobe signal C
The first address signal supplied in synchronization with the change of AS from high level to low level is taken into the start address register SAR. Although not particularly limited, an end address signal supplied in synchronization with the timing at which the column address strobe signal CAS changes from low level to high level is supplied to the first end address register EAR1. At this time, the previously set valid end address signal is supplied to the second end address register EAR2.

Then, as described above, before the signal RAS falls, the signal DT10E is set to low level to set the data transfer mode. At this time, read transfer or write transfer is performed depending on the high level or low level of the write enable signal WE when the signal RAS falls. For this transfer, an address signal supplied in synchronization with the fall of the signal CAS is taken into the start address register SAR as a start address signal. Then, the address signal supplied at the timing when the signal CAS changes from low level to high level is taken into the first end address register EAR1 as an end address signal for the next cycle. In synchronization with this operation, the end address signal taken in in the dummy cycle is transferred to the second end address register EAR2.

Therefore, in this operation mode, serial access corresponding to the area of the memory array M-ARY specified by the start address and the end address fetched in the dummy cycle is possible. Memory array M
Data transfer from ARY to latch circuit DFF (read data transfer) or data transfer from latch circuit DFF to memory array M-ARY (write data transfer) is performed.

Prior to or following this data transfer, continuous data input or output is performed by the shift register.

In Figure 3? The serial output operation is synchronized with the clock signal CLK by setting the serial output operation mode with the end address captured by the dummy cycle as described above, which shows an example of continuous serial output over several word lines. I do.

In other words, before the end of this serial output operation,
In parallel with this serial output operation, when the row address strobe signal RAS is changed from high level to low level, the row address signal RA is taken into the row address buffer R-ADB. As a result, the word line of the memory array M-ARY to be read next is selected.

At this time, before changing the signal RAS to low level,
The data transfer and output enable signal DT10E is set to low level to indicate the transfer mode. Therefore, the memory information of the memory cell coupled to the word line to be read next is amplified by the sense amplifier and output as complementary data of the memory array M-ARY. This signal is taken into the first latch circuit PDFF via the transfer gate circuit TFG1.

Next, the address signal SA supplied in synchronization with the change of the signal CAS from high level to low level is taken into the start address register SAR as a start address signal for the next serial output operation. At the end of this operation, signal DT10E is returned to high level.

On the other hand, the address counter C0UNT counts the column addresses in the above serial output operation, and the comparator circuit DCMP performs a comparison operation with the previously captured end address (second end address register EAR2). .

When both of the above signals match, an end signal END is formed. The period until the end signal END is formed is the serial output operation period of the current data.

Therefore, the time T1 from when the signal RAS is set to low level until the end signal END is output is as follows:
It is necessary that the time required for the word line selection operation of the memory array M-ARY and the amplification operation of the sense amplifier be the minimum required time. Note that if the above-mentioned time T1 is set long, the time during which random access is possible will be shortened, so it is desirable to set the above-mentioned time T1 to the minimum necessary time.

During the time T2 after the current data is output to the output circuit SIO until the new data is serially output, the data taken into the first latch circuit PDFF is transferred to the second latch circuit DFF.

Also, the start address signal SA taken into the start address register SAR is sent to the column decoder C-D.
It is decoded by CR and the initial value of the shift register SR is set. As a result, the new data is serially output in synchronization with the clock signal CLK.

Then, after the new data serial output operation has started,
By changing the signal CAS from low level to high level,
The end address signal for the next cycle is taken into the first end address register EAR1, and the end address signal already taken into this first end address register EAR1 is transferred to the second AND address register E.
Transferred to AR2. Thereafter, pixel data of a certain area in the memory array M-ARY is serially output by a similar operation.

Note that when data transfer is performed without changing the start address and end address, the signal CAS remains at a high level. Furthermore, in the case of a write transfer operation in which the write enable signal WE is set to a low level, although not shown, the information stored in the second latch circuit DFF is transferred to the memory array M-ARY by the low level of the signal RAS. Prior to this write transfer, -
Writing is performed only to the bits of the second latch circuit DFF corresponding to a certain Airy. When this serial input operation is performed up to the address corresponding to the end address, the end signal END returns to the start address. As a result, only data in a certain area that is desired to be rewritten can be rewritten.

In this embodiment, the signal D T10 E is changed from a low level to a high level at an appropriate timing, and a serial operation corresponding to the next word line is performed according to the internal signal END, so that the timing margin of the external signal to the internal circuit is reduced. can be made free.

In this way, when giving the start address and end address of serial output, the column decoder C-
Since the DCR is common to the switch circuits ssw and CSW, the common data line for random access is connected to the complementary data line. However, this column decoder C-
While the DCR can be made common and its configuration can be simplified, mode identification does not cause the same inconvenience.

Note that in the serial input/output operation by the latch circuit DFF and shift register SR, the memory array MA
Since RY and its peripheral circuits are inactive, in parallel, the signals RAS and CAS are temporarily set to high level.
When set to low level again, 1 bit (or 4 bits)
Writing/reading can be performed by random access upon accession to the throne.

FIG. 4 shows a circuit diagram of another embodiment regarding the unit shift register USR shown in FIG. A start point latch circuit 5PRO, an end point latch circuit EPRO, and a next end point latch circuit NEPRO are provided between the output signal line and the unit shift register USR'. Each of the above latch circuits is connected to a pair of inverter circuits ( N?, N8), (N 9. N 10) and (Ni
l.

N12). In order to specify the input timing and output timing to each latch circuit, the control signal φ
Switch MO controlled by 5etl~φ5wt4
3FETs Q16 to Q19 are provided.

The configuration between the other output signal lines of the column decoder C-0CR and the corresponding unit shift registers is also similar to the above configuration. That is, the output signal line to which the output signal Y1 is supplied has a start point latch circuit 5PR1.
, an endpoint latch circuit EPR1, and a next endpoint latch circuit NEPR1. Also,
Each latch circuit is constituted by a pair of inverter circuits, and in order to define the input timing and output timing to each latch circuit, the control signals φ5etl~
Published 4 times by φ5wt4 switch MO3FE
TQ20-Q23 are provided. The information held in each start point latch circuit (SPRO, 5PRL, . . . ) is determined based on the AT female signal transferred from the START AT I/S register SAR.

End point latch circuit (EPRO, EPRl...
The information held in the previous stage next end point latch circuits (NEPRO.

NEPRI...) at a predetermined timing. Each next end point latch circuit (NEPR
The information held in the registers (O, NEPRI, . . . ) is determined based on the address signal sent from the end address register EAR1 or EAR2. The output signal of the end point latch circuit EPRO is the N
It is used as an input signal to the AAND circuit NA. Unit shift register tJ S )'? When the shift operation of the shift register is to be terminated at ', the output signal of the endpointer and Jchi circuit EPRO corresponding to the shift register SR' of this unit is set to low level. Therefore, the output signal of the NAND circuit NA is fixed at a high level. As a result, the operation of shifting the selection level to the switch circuit SW is stopped.

The effects obtained from the above embodiments are as follows. That is, 11) A signal path that transmits signals in parallel to the data line of the memory array and the latch circuit, and a selection signal formed by a ring-shaped shift register that connects the latch circuit and a common data line for serial input/output. In addition to providing a switch path for connection, the column decoder can be used for random input/output and for serial Can be shared for input and output. by this,
Serial input/output and random input/output are possible, and the effect is that the circuit for communication can be converted to 5G.

(2) By supplying the end address signal for the current serial operation mode and the end address signal for the next cycle to the respective registers, multiple pieces of data constituting a certain area specified by the start address and end address can be stored. The effect is that serial input/output can be performed continuously across word lines.

(3) Due to +11 and (2) above, it is possible to perform serial input/output by specifying an arbitrary address to the memory array M-ARY, which has a large storage capacity relative to the number of pixels that make up the CRTi surface. The effect of speeding up various image processing can be obtained.

(4) By the internal end signal, the serial sensor 1"
Since the end of the serial cycle and the start of the next serial cycle can be automatically switched, the timing margin of the externally supplied control signal instructing the speed reading serial mode can be virtually freed. It will be done.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, the end signal may be used to substantially stop the shift operation of the shift register SR. In order to achieve t+ti kil of such a shift operation, it is sufficient to stop the supply of the clock signal φS or to provide a gate circuit controlled by an end signal between each unit circuit constituting the shift register.

In FIG. 1, the memory array M-ARY and its peripheral circuits may be arranged symmetrically with respect to the column decoder. In this case, the shift clock signal CLK can be input or output alternately for odd and even numbers, so the actual operating speed of internal circuits such as shift registers can be controlled by clocks). The frequency can be slowed down to 1/2 of the frequency.

Furthermore, the memory array M-ARY may perform the memory cell selection operation using a so-called shared sense amplifier method in which memory arrays are arranged on the left and right sides of a sense amplifier.

In addition, the reference voltage used to read information stored in a memory cell can be obtained by precharging a complementary data line to a potential Vcc/2, which is 1/2 of the power supply voltage Vcc, in addition to using a dummy cell. A half precharge method or a dummy cellless method may be adopted.

Further, the memory array may be configured using static type memory cells in addition to the type using dynamic type memory cells as described above.

This invention can be widely used in semi-external memory '2W having random input/output functions and serial input/output functions.

〔Effect of the invention〕

The effects obtained by typical inventions disclosed in this application are as follows. That is, a first latch circuit that transmits and receives signals in parallel with the data line of the memory array according to a first transfer timing signal for serial input/output;
a second latch circuit that transmits and receives signals in parallel with the memory array or the first latch circuit according to a second transfer timing signal; and a second latch circuit that transmits and receives signals in parallel with the first or second latch circuit; A switch circuit for serial input/output provided between the serial input/output line, a start address register to which a start address signal is supplied, and a column decoder decoding the address signal supplied to this start address register. a shift register to which a signal is supplied as an initial value and whose shift operation forms a selection signal for the serial input/output switch circuit;
first and second end address registers to which first and second end address signals are supplied, respectively;
an address counter whose initial value is set by the start address register and counts serial input/output operations by the shift register; an output signal of the address counter and the first or second end address. A comparison circuit is provided to receive the output signal of the register, and when the serial data input/output operation starts from the address specified by the start address register, it is A serial input/output operation is performed up to the specified address, and in parallel with this serial input/output operation, an end address signal for the next operation cycle is taken into the second or first end address register, and the next A memory array signal to be input/output in an operation cycle is taken into the first or second latch circuit. As a result, initial addresses for random input/output and serial input/output can be decoded using a common column decoder, and a certain range of data can be designated from among the word lines of the memory array for serial input/output. Can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of each circuit for random input/output and serial input/output operation, and FIG. 4 is a timing diagram showing an example of its operation, and FIG. 4 is a circuit diagram showing another embodiment of the present invention. M-ARY...Memory array, R-ADB...Row address buffer, C-ADB...Column address buffer, R-DCR...Row address decoder, C-DC
R: Column address decoder, C3W: Column switch circuit, SSW: Serial transfer switch circuit, P
DFF, DFF...data latch circuit, S R&S
SW...Serial selection circuit, Ilo...Random input/output circuit, SIO...Serial output circuit, TFGI, T
FG2...Transfer gate circuit, RAR...Random access address register, SAR...Start address register, EAR1, EAR2...End address register, C0UNT...Address counter, D CMP...
Comparison circuit, TC...timing control circuit, UC3W, P
T,! DFF, UDFF, USR...unit circuit

Claims (1)

[Claims] 1. A column switch circuit for random input/output provided between a data line constituting a memory array and a first common data line, and a column forming a selection signal for the column switch circuit. a decoder circuit; a first latch circuit that transmits and receives signals in parallel between data lines of the memory array according to a first transfer timing signal; a second latch circuit that sends and receives signals to and from the circuit in parallel; and a switch circuit for serial input/output provided between the first or second latch circuit and a second common data line. and a start address register to which a start address signal is supplied, and a signal formed by decoding the address signal supplied to this start address register by the column decoder and supplied as an initial value, and the shift operation causes the serial input/output to be performed. a shift register that forms a selection signal for the switch circuit for the switch circuit; a start address register to which a start address signal is supplied; and first and second end address registers to which first and second end address signals are supplied, respectively. , an address counter whose initial value is set by the signal of the first end address register and the start address register and which counts serial input/output operations by the shift register; an output signal of the address counter and the first or first end address register; and a comparison circuit that receives the output signal of the second end address register, and when a serial data input/output operation is started from the address specified by the start address register, the first or second end that has already been written is A serial input/output operation is performed up to the address specified by the address register, and in parallel with this serial input/output operation, an end address signal for the next operation cycle is taken into the second or first end address register. . A semiconductor memory device, wherein a memory array signal to be input/output in the next operation cycle is taken into the first or second latch circuit. 2. The corresponding unit circuits constituting the first and second latch circuits and the first and second end address registers are connected in a cascade configuration via a transfer gate circuit, and are connected to new data. The current data, the end address signal of the current cycle, and the end address signal of the next cycle are transferred in accordance with the timing signal formed according to the output signal of the comparison circuit, so that the new data becomes the current data and the end address signal of the current cycle becomes the current data. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device replaces the end address signal of the next cycle.