JPS61182694A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide various functions by external control signals by using a construction in which a mode control circuit is provided and its operating mode is designated by mode control signals supplied from external. CONSTITUTION:When a signal indicating the operating mode is supplied from external terminals C1, C2 to a mode control circuit MODE of a dynamic type RAM, a timing generator TG and a refresh control circuit RFFC are started in accordance with control signals. For example, with respect to the refresh control circuit RFFC, a multiplexer MPX is changed over and the inner address signals from an incorporated refresh address counter is transmitted to a low decoder R-DCR to effect a refresh operation by a sole word line selection. Alternatively, continuous refresh operation is carried out at each constant period. With respect to the timing generator TG, control signals selectively inhibiting the write operation, for example, are formed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
Dynamic RAM (Random access memory 1
It is about technology that can be used effectively on the moon.

[Background technology]

With the expansion of applications for dynamic RAM, models with various functions have been developed. method (for example, “Electronic Technology 1 Magazine Vo123
, N13, pp3o-33), a method is considered in which refresh is performed asynchronously with the external device according to the cycle of a built-in timer, and a busy signal is generated during the refresh. Conventional dynamic RAM has been designed to have one of the above functions, so manufacturers have to create a wide variety of products, which impairs mass production, while users have problems with the system. This will result in restrictions on the changes made.

-2 [Objective of the Invention] An object of the present invention is to provide a semiconductor memory device that has various functions according to external control signals.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the mode of operation is specified according to a mode control signal supplied from the outside.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a dynamic RAM.

Each circuit block in the figure is formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques, but is not particularly limited.
Terminals Din, Dout, AO~A17. W.E., C.
3, REF, C1, C2, and Vcc and Vss are external terminals, and power is supplied to the terminals Vcc and Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array, in which well-known 1MO3 type memory cells composed of storage capacitors and address selection MOS FETs are arranged in a matrix, as will be described later. . In this embodiment, the memory cell is constructed in a two-intersection manner in which its input/output node is coupled to either one of a pair of complementary data lines D arranged in parallel.

The circuit indicated by the circuit symbol PC is a data line precharge circuit. The precharging operation of the memory array of this embodiment is carried out by simply shorting a pair of complementary data lines (the same applies to a common complementary data line to be described later) using a MOSFET. This is an intermediate level. As a result, compared to a charge amplifier that charges from O volts to Vcc level, the amount of level change is small, and even if the gate voltage of the precharge MO3FET is used at a normal logic level (Vcc), it can be turned on in a sufficiently unsaturated state. The precharge operation that can be performed can be performed at high speed and with low power consumption. As mentioned above, set the precharge level to about V
Since it is set to an intermediate level of cc/2, even when reading the memory cell, the memory cell switch MO
Even if a normal logic level (Vcc) is used as the gate voltage (word line selection voltage) of the 3FET, it can be turned on in a sufficiently unsaturated state, so the entire charge of the information storage capacitor can be read out without using a bootstrap voltage. becomes possible. Furthermore, by using the precharge level of one data line on which no memory cell is selected as the read reference voltage, a dummy cell that forms the read reference voltage is not required.

What is indicated by the circuit symbol SA is a sense amplifier, which, although not particularly limited, has a pair of power amplifiers each consisting of a P-channel inter-channel O3FET and an N-channel MO3FE'r at the power supply voltage Vcc and the circuit ground potential Vss. 0MO5 (complementary type M
O3) It is composed of a launch circuit, and its pair of input/output nodes are coupled to the complementary data line D. The timing pulse φpa is the power switch MO3FET
The purpose is to control the In addition, N channel MO
In order to control the power switch MOS FET composed of the 3FET and the P-channel O3FET, a non-inverted timing pulse φpa and an inverted timing pulse φpa are used.
However, in the figure, the non-inverted timing pulse φ
Only pa is shown. The above pair of power switches M
The OS FET is turned off immediately before the start of the precharge operation described above. This creates a complementary data line, D&
The Vcc and Vss levels are maintained in a floating state.

The circuit symbol C-5W is a column switch, which connects a selected complementary data line to a common complementary data line (represented by one line) CD, CD according to a column selection signal.
be combined with

The circuit symbol R-ADB is a row address buffer which receives external address signals from external terminals AO to A8 and outputs internal complementary address signals aO to a8 . a
Form o-a8. In addition, in the following explanation and drawings,
A pair of internal complementary address signals, for example 801-0, will be expressed as internal complementary address signal U0. therefore,
The internal complementary address signal aQ-a9. aQ to a8 are
The internal complementary address signals are expressed as 10 to 8.

The circuit symbol C-ADB is a column address buffer that receives external address signals from external terminals A9 to A17 and outputs internal complementary address signals a9 to a.
1? +a Form 9-17. In addition, in accordance with the method of representing the internal complementary address signals described above, in the drawings and the following description, the internal complementary address signals a9 to a1 are
7. a9 to 17 internal complementary address signals upper 9 to mutual 17
Expressed as

The circuit symbol R-DCR is a row address decoder, which receives internal complementary address signals 10 to i8 or 10° to 8 (total 8) through a multiplexer MPX, which will be described later, to M-A R'. A Y word line selection signal is formed. This word line selection signal is transmitted to M-ARY in synchronization with the word line selection timing signal φX.

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier SA described above.

The circuit symbol DOB is a data output cover sofa, which sends read data from the main amplifier MA to an external terminal I10 in response to a timing pulse φr-. Note that during writing, this data output buffer D is activated by the low level of the timing pulse φr-.
OB is placed in an inactive (output high impedance) state.

What is indicated by the circuit symbol DIB is the data driver cover sofa, which is connected to the external terminal I by the timing signal φri1.
10 is transmitted to the common complementary data line.

Note that during reading, this DIB is rendered inoperable in the same manner as described above by the low level of the timing signal φrH. Thereby, if necessary, the terminals Dout and Din can be connected to a common external data bus. In addition,
The terminals Dout and Din may be a common terminal.

The various timing signals described above are formed by the following circuit blocks. .

Although not particularly limited, the circuit symbol RATD is an address signal change detection circuit that receives address signals aO to a8 (or 0 to 8) and detects a change in their rising or falling edge. What is indicated by the circuit symbol CATD is an address signal a, although it is not particularly limited.
This is an address signal change detection circuit that receives signals 9 to a17 (or 9 to 17) and detects a change in the rising or falling edge thereof.

The address signal change detection circuit RATD includes, but is not particularly limited to, an exclusive OR circuit that receives each of the address signals aO to a8 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. It is composed of That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of these nine (1M exclusive OR circuits) are input to the OR circuit. 'signal aO
When any one of ~a8 changes, an address signal change detection pulse φrt synchronized with the change timing
- form.

The address signal change detection circuit CATD has the same configuration as the address signal change detection circuit RAT". That is, an exclusive OR circuit that receives address signals a9 to a17 and their delays (No. 8), respectively. and an OR circuit that receives the output signals of these exclusive OR circuits.This address signal change detection circuit CATD is composed of the above-mentioned address signal change detection circuit RA'.
Similarly to l'D, when any one of the address signals a9 to 317 changes, an address signal change detection pulse φC synchronized with the timing of the change is formed.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. That is, this timing generation circuit TG
receives address signal change detection pulses ψr, φC, write enable signal WE and chip selection signal τ, which are supplied from external terminals, and performs the above-mentioned series of timing pulses and serial read operation of memory array M-ARY, which will be described later. form the timing pulses necessary for This timing generation circuit TG is connected to a mode control circuit MO as described later.
Changes in its operation are made according to the operating mode signal indicated by the DE.

The dynamic RAM of the illustrated block constitutes a static RAM. Various circuit operations are controlled by detection pulses φr and φC sent from address signal change detection circuits RATD and CA 'I'D.

When a detection pulse φr is output in response to a level change in at least one of the row-related internal address signals output from the multiplexer MPX, which will be described later, the timing generation circuit TG controls the operation of the row-related circuits accordingly. A timing signal is output. When the detection pulse φr is generated, the timing signal φpa is set to a level that disables the sense amplifier SA in response to the generation of the detection pulse φr.

The timing signal φp is set to a high level precharge instruction level for a predetermined period from the same time as the timing signal φpa is changed or at a slightly delayed timing. This activates the precharge circuit PC,
Each data line in memory array M-ARY is VVc.
Precharged to c72 level. That is, preparations are made before the data read operation.

The timing signal φX is set to a low level, for example, in synchronization with the detection pulse φr, and is set to a high level after the timing signal φp is set to a low level.

Row decoder R-DCR is operated by setting timing signal φX to high level.

As a result, one of the plurality of word lines in memory array M-ARY corresponding to the row-related internal address signal is selected.

The timing signal φpa is set to a level that operates the sense amplifier SA after the timing signal φX is set to a high level. As a result, the data read from the memory cells in the memory array M-ARY starts to increase.

The timing signal φy is set to a low level when the detection pulse φr is generated, and is set to a high level after the timing signals φX and φpa are generated.

When the detection pulse φC is generated while the timing signal φX is set to high level, the timing signal φy becomes the low level or the set level for a predetermined period from that time, when the low address signal is changed. After being raised to a high level. Column decoder C-
The DCR is operated by setting the timing signal φy to a high level. Column switch C-5W is activated by the operation of column decoder C-DCR. As a result, one of the plurality of pairs of data lines in memory array M-ARY corresponding to the column address signal is selected.

The timing signal φma is set to a low level in synchronization with the timing signal φy set to a low level, and is set to a high level after the timing signal φy is set to a high level. Main amplifier MA is operated by setting timing signal φma to high level.

The timing signal φTH is generated when the chip selection signal at the external terminal C8 is set to a low level (selection level) and the write enable signal at the external terminal WE is set to a high level (
For example, when the read operation instruction level is set to the low level.

The circuit symbol MPX is a multiplexer, which controls the address buffer R according to a control signal (not shown) from an automatic refresh circuit REFC, which will be described later.
- Internal complementary address signal ao-a8 formed by ADB
and internal complementary address signals Q I to i81 formed by the automatic refresh circuit REFC are selectively transmitted to the decoder R-DCR.

The circuit symbol REFC is an automatic refresh circuit, which includes a fresh address counter, a timer, and the like. This automatic refresh circuit REFC receives a refresh signal REFC from an external terminal, for example, according to a control signal supplied from a mode control circuit MODE.
It is activated by making the low level. That is,
When the refresh signal Tτ is set to low level when the chip selection signal C5 is high level, the automatic refresh cycle i
REFC switches the multiplexer MPX, transmits an internal address signal from a built-in refresh address counter to the row decoder R-DCH, and performs a refresh operation (auto-refresh) by selecting one word line. Further, when the refresh signal REF is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this period. Alternatively, a built-in timer circuit causes the refresh operation to be performed at regular intervals regardless of the external circuit.

In such a refresh operation, the external terminal REF is set to a low level during the refresh period, and a message to that effect (busy) is sent to the outside.

Although not particularly limited, the mode control circuit MODE receives signals instructing the operation mode supplied from the external terminals C1 and C2, and controls the timing generation circuit TG and the refresh control circuit REFC to control the refresh control, for example. The circuit REFC is caused to execute one of the two refresh methods described above.

Furthermore, the mode control circuit MODE changes the self-refresh cycle in the synchronous refresh operation and the refresh cycle in the asynchronous refresh operation by, for example, changing the set time of a timer circuit for the refresh control circuit REFC. make it change

On the other hand, the mode control circuit MODE generates a control signal for selectively inhibiting the write operation, for example, to the timing generation circuit. That is, by inhibiting the generation of the operation timing signal φr- of the data driver sofa DIB, writing is not performed even if the write enable signal WE is set to a low level, for example. Such functions, for example, use the memory area where the program is written as a data area,
This is useful for preventing a computer from running out of control or from data loss due to a programming error such as writing in an area where important data has been written. Note that, if there is a write access to the RAM for which write prohibition has been specified, it is desirable to also provide a function to send out a notification to that effect from an appropriate external terminal.

In addition, a switch circuit is provided that internally makes the external terminals Din and Dout common, and the mode control circuit MO
The DE is used for selective switching.

As mentioned above, by the 2-bit control signals CI and C2,
The above four functions can be selected.

The above mode control circuit MODE is configured with a shift register, and a plurality of bits of control signals are serially supplied from one external terminal to select more functions with fewer terminals, or an address terminal is configured to select more functions with fewer terminals. On the other hand, even if the mode control signal is supplied at a level higher than the input high level during normal operation at a power supply voltage Vcc or higher, the mode control signal is supplied without substantially increasing the number of external terminals. It is possible to supply the signal supplied to the data or address terminal to the internal circuit by applying an input higher than the input high level during normal operation to the control terminal such as WE or C3, and use it as a mode control signal. In this case, the internal circuit may have a memory function, and either a nonvolatile memory element or a volatile memory element may be used.

Furthermore, a plurality of data output circuits and data input circuits may be formed so that access can be performed in units of one bit or in units of multiple bits. Furthermore, when accessing in units of multiple bits, the function for parallel input/output and the function for serial transmission may be switched.

〔effect〕

(1) By providing a mode control circuit and selectively switching multiple functions, manufacturers can improve mass productivity, and users can easily change the system. is obtained.

(2) Since the mode control circuit is provided to change the function, the function can be changed by software.

This has the effect that it is possible to implement functions that match the usage pattern of memory at any given time.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the address signal may be multiplexed and supplied as a row address signal and a column address signal in synchronization with an address strobe signal from a common external terminal. In this case, it is conceivable to provide a function for switching between page mode and nibble mode as continuous access operations performed using address strobe signals. The mode control signal supplied to the mode control circuit may be formed by software, an external switch, or a jumper wire connected to the ground potential or power supply voltage terminal. good.

[Application field]

In addition to dynamic RAM, this invention also applies to static RAM and various read-only memories (R
It can be widely used in various semiconductor memory devices such as OM).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. M-ARY...Memory array, PC...Precharge circuit, SA...Sense amplifier, R-ADH...Row address buffer, C-5W...Column switch, C-ADB
・・Column address buffer, R-DCR・・Row address decoder, c-DCR・・Column address decoder, MA・・Main amplifier, RATD, CATD・−Address signal change detection circuit, TG・・Timing generation circuit,
REFC: automatic refresh circuit, DOB: data output cover sofa, DIB: data input cover sofa, MPX
...Multiplexer, mode control circuit Figure 1

Claims (1)

[Scope of Claims] 1. A semiconductor memory device characterized in that its operation mode is specified in accordance with a mode control signal supplied from the outside. 2. The semiconductor memory device according to claim 1, further comprising a circuit for storing a mode control signal supplied from the outside, and designating an operation mode according to an output signal of the circuit. 3. The semiconductor memory device is a dynamic RAM, and one of the operating modes is switching between a refresh operation performed in synchronization with an external control signal and a refresh operation performed independently according to an internally generated address signal. A semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a RAM, and one of the operation modes is an operation of selectively disabling a write operation.