JPS59136970A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59136970A JPS59136970A JP1182183A JP1182183A JPS59136970A JP S59136970 A JPS59136970 A JP S59136970A JP 1182183 A JP1182183 A JP 1182183A JP 1182183 A JP1182183 A JP 1182183A JP S59136970 A JPS59136970 A JP S59136970A
- Authority
- JP
- Japan
- Prior art keywords
- section
- wiring
- contact
- film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- -1 boron ions Chemical class 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 239000011733 molybdenum Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 230000001954 sterilising effect Effects 0.000 description 1
- 238000004659 sterilization and disinfection Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、配線部と、配線と拡散層との接触部とがシリ
サイドである。栄導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION In the present invention, the wiring portion and the contact portion between the wiring and the diffusion layer are made of silicide. This relates to Sakae conductor equipment.
従来、浅い拡散層を形成するために、イオン注入法が使
用さｎでいる。最近の半導体果績回路装置では、拡散の
深さを浅くすると、層抵抗が高くなってしまう。例えは
、ホウ素イオン注入法でＮ型シリコン基板に、拡散の深
さ０．５μｍのＰ型拡散層を、形成しよりとすると、拡
散層の層抵抗は単純に１００Ω／口と高くなってしまう
。イオン注入条件を最適化し、イオン注入法の電気的溶
性化のだめの熱処理条件を低温短時間化しても、層抵抗
は５０Ω／口 程度しか低下しない。又、従来、配線層
はＡ１が使用されてお９、多層配線化のためには、多結
晶シリコンが用いられてきた。多結晶シリコンを配線と
して使用する場合、画濃度のリンを添加したものでも比
抵抗はｉ ｘ ｉ ｏ−３Ω・副と商くなってし甘い、
配線４延の問題がうり、又、多結晶シリコンのため、微
細加工の９えで、不適当てあった。Conventionally, ion implantation is used to form shallow diffusion layers. In modern semiconductor circuit devices, shallower diffusion depths result in higher layer resistances. For example, if a P-type diffusion layer with a diffusion depth of 0.5 μm is formed on an N-type silicon substrate by boron ion implantation, the layer resistance of the diffusion layer will simply be as high as 100Ω/hole. . Even if the ion implantation conditions are optimized and the heat treatment conditions for electrical solubility in the ion implantation method are lowered and shortened, the layer resistance will only decrease by about 50Ω/hole. Furthermore, conventionally, A1 has been used for wiring layers9, and polycrystalline silicon has been used for multilayer wiring. When polycrystalline silicon is used as wiring, even when phosphorus is added to the picture density, the specific resistance is ix io-3Ω.
There was a problem with the length of the wiring, and since it was made of polycrystalline silicon, there was an inappropriate fit in the 9th step of microfabrication.
不発明は、上記欠点を解決じたものでリラ、配線御と配
縁と拡散層の接触部（以下、コンタクト部と呼ぶ）の両
方をシリサイド化し、配線の比抵抗を下げ、コンタクト
部の層抵抗を下げた、微細加工に適した半導体装置であ
る。The invention solves the above-mentioned drawbacks by siliciding both the wiring control and the contact area between the wiring and the diffusion layer (hereinafter referred to as the contact area), lowering the specific resistance of the wiring, and reducing the contact area layer. This is a semiconductor device with low resistance that is suitable for microfabrication.
次に７本発明を図囲Ｃヒより詳細に説明する。説１９」
を簡潔にするため、半導体装置の中で、ＰチャネルＭＯ
Ｓ ４ｊｌ トランジスタ装置について説明する。Next, the present invention will be explained in detail from Figure C. Theory 19”
In order to simplify the process, P-channel MO
The S 4jl transistor device will be explained.
矛１図において、Ｎ型Ｓｉ基板１に、熱酸化５ｉ１１＠
２ ’Ｔ ５０００ ＡＬｖ族厚で形成１−る。次に、
従来の７オトエンチング法で、ＭＯ８ｆｆｉ）ランジス
タのゲート部となる部分の熱酸化Ｓし膜を除去し、熱師
化法で、１度厚５００Ａのケート秦化Ｓ１膜６を形ｊｊ
ｙする。」７２図において、フォトエンチング法で、最
終的にソース・ドレーンとなる拡散層と配線との接触部
４（コンタクト部）を形成する。In Figure 1, the N-type Si substrate 1 is thermally oxidized 5i11@
Formed with 2'T 5000 ALv thickness. next,
Using the conventional etching method, remove the thermally oxidized S film on the part that will become the gate part of the MO8ffi transistor, and then form the Kate Qin Chemical S1 film 6 with a thickness of 500A once using the thermal sterilization method.
Do y. 72, a contact portion 4 (contact portion) between the wiring and the diffusion layer, which will eventually become the source/drain, is formed by photo-etching.
次に、到・６１ネ］において、高融点戦域の１つである
モリブテンＭｏ膜５を、厚さ２１１０ｏＸ、スパッタで
形成する。ＭＯの形成はＣＶＤ法でも可能でめる。ざら
に、ＣＶＤ法で５１０２膜６を、厚さ３ＱＯＯＸ形成す
る。この５１０２膜は、仄の工程で欧明惰るように、Ｓ
ｉイオン注入する時のマスク材料となるものでるる。次
に、矛４図に示すように、フォトエツチング法で。シワ
サイド化テベき配線部７とコンタクト部８の領域のＭＯ
が露田するように、ＣｊＶＤの５ｉ０２膜を除去づ−る
。配線部７の一部分に、ＰチャネルＭＯ８型トランジス
タのケート部分でもあ冷。次に、矛５図に示すように、
Ｓｉオン９ケ、エネルギー４０ＫｏＶ、 ドーズ量ｂ
Ｘ １０” ／ｃ４ の条件でイオン注入する。こ
；ＬＬによって、シリサイド化でれた配線部７ａ（Ｐチ
ャネルＭＯ８型トランジスタのゲート部７ｂを苫む）と
、同じく、シソサイド化されたコンタクト部１０とが得
らｎる。１７６図のように、マスクＢｉＯ２６を除去し
たあとで、マスクＢ ｉ Ｑ２の下にめったＭｏ層を除
去することによりシリサイド化した配線部７ａ（ゲート
部７ｂを含む）と、コンタクト部１０を形成するととが
でさる。最後に、オフ図に示すように、ホウ素イオン１
１を、エネルギー２０ＫｅＶ、 ドーズ量５ Ｘ １
０”／ｃｒｄの条件でイオン注入づ−ると、Ｐチャネル
Ｍ ＯＳ型トランジスタのンース都１２とドレーン都１
６とかＰ型拡故層に変化する。この後で、熱処理を行な
い、ソース郁１２．ドレーン部１６と、自己線部７ａ、
ゲート部７ｂすべてが、完全なシリサイドとなる。Next, in [61], a molybdenum Mo film 5, which is one of the high melting point films, is formed by sputtering to a thickness of 2110°. MO can also be formed by CVD. Roughly, a 5102 film 6 with a thickness of 3QOOX is formed using the CVD method. This 5102 membrane is made of S.
This material is used as a mask material for i-ion implantation. Next, as shown in Figure 4, photo-etching was performed. MO in the area of the wrinkled tapered wiring part 7 and the contact part 8
The CjVD 5i02 film is removed so that it is exposed. A portion of the wiring section 7 is also cooled at the gate of the P-channel MO8 type transistor. Next, as shown in Figure 5,
9 pieces of Si-on, energy 40KoV, dose amount b
Ion implantation is performed under the condition of X 10''/c4. By LL, the wiring portion 7a which has been made into a silicide (the gate portion 7b of the P-channel MO8 type transistor is torn) and the contact portion 10 which has also been made into a silicide. As shown in Fig. 176, after removing the mask BiO26, the Mo layer below the mask B i Q2 is removed to form the silicided wiring part 7a (including the gate part 7b). , when the contact portion 10 is formed, a sharp edge appears.Finally, as shown in the off-line diagram, boron ions 1
1, energy 20KeV, dose 5 x 1
When ions are implanted under the condition of 0''/crd, the source capital 12 and drain capital 1 of a P-channel MOS transistor are
6 or P-type spreading layer. After this, heat treatment is performed to prepare the sauce.12. a drain part 16, a self-line part 7a,
The entire gate portion 7b becomes complete silicide.
この結果、ソース・ドレインのコンタクト部の層抵抗は
１０Ω／口以下と低くなり、ＰチャネルＭＯＳトランジ
スタのゲート部、配線部の比抵抗もｌＸ１０−’Ω副と
１炊くなる。As a result, the layer resistance of the source/drain contact portion is as low as 10 Ω/or less, and the specific resistance of the gate portion and wiring portion of the P-channel MOS transistor is also reduced to 1 × 10−′ Ω.
このように、本発明によれば、拡散層がイオン注入法等
による浅い接合深δのものであっても、［広散層と配線
のコンタクト部の層抵抗は、従来のものより一佑低く、
又、配線部の比抵抗も、従来のものより一桁低くするこ
とが可能となる。As described above, according to the present invention, even if the diffusion layer has a shallow junction depth δ formed by ion implantation, the layer resistance of the contact portion between the diffusion layer and the wiring is a little lower than that of the conventional one. ,
Furthermore, the specific resistance of the wiring portion can be lowered by one order of magnitude compared to the conventional one.
ここでは、ＰチャネルＭ ＯＳ型トランジスタＶＣつい
て、費明したが、ＮチャネルＭＯ８型トランジスタ、又
、バイポーラ型トランジスタであっても同様の効果が得
ら九るものである。Although a P-channel MOS type transistor VC has been explained here, similar effects cannot be obtained with an N-channel MO8 type transistor or a bipolar type transistor.
ざらに、シリサイド化さｎる材料としてＭＯを代表例と
じて示したが、その他のシリサイド化可能な元素′Ｔ：
あれは、同一の効果が得られることはに９甘でもない。In general, MO is shown as a typical example of a material that can be silicided, but other elements that can be silicided:
It's not at all likely that you'll be able to get the same effect.
第１図はゲート酸化膜ブレ成後の断■図、２・２図はコ
ンタクト形成後の断■図、オ１５図はＭｏ 。
ＯＶＤ ＳｉＯ□形成後の断■図、第４図はシリサイ
ド化するためのマスク形ｆｊＸ、佐のＩＢｏ１図、真・
５図はＳ１イオン注入によるシリサイド形成後の断面図
、矛６図はマスタ５ｉ０２．Ｍｏ 除去後の断面図、
オフ図は、シリサイドＰチャネルＭＯ８型トランジスタ
の断面図である。
１・・・Ｎ型Ｓ１基板、 ２・・・熱酸化膜、６・・
・ゲート酸化膜、 ４・・・コンタクト部、５ ・−
Ｍｏ ？ＩＡ、 ６ ・・・ＯＶ Ｄ ５ｉ
Ｏｚ膜。
７・・・配ｍｓ、 ８・・・ＭＯのコンタク
ト部、９・・・Ｓ１イオン・
７ａ・・・シリサイド化配線部、
７ｂ・・・シソサイド化ゲート部、
１０・・・シリサイド化コンタクト部、１１・・・ホウ
素イオン、
１２・・・ＭＯ８型トランジスタの′ノース、１６・・
・Ｍ ＯＳ型トランジスタのドレーン。
第２図
第３図Figure 1 is a cross-sectional view after forming a gate oxide film, Figures 2 and 2 are cross-sectional views after forming a contact, and Figure 15 is a cross-sectional view of Mo. A cross-sectional view after OVD SiO
Figure 5 is a cross-sectional view after silicide is formed by S1 ion implantation, and Figure 6 is a cross-sectional view of the master 5i02. Cross-sectional view after Mo removal,
The off view is a cross-sectional view of a silicide P-channel MO8 type transistor. 1...N-type S1 substrate, 2...thermal oxide film, 6...
・Gate oxide film, 4... Contact part, 5 ・-
Mo? IA, 6...OV D 5i
Oz membrane. 7... Connections, 8... MO contact part, 9... S1 ion, 7a... Silicided wiring part, 7b... Silicided gate part, 10... Silicided contact part, 11...Boron ion, 12...'north of MO8 type transistor, 16...
・MOS type transistor drain. Figure 2 Figure 3
Claims (3)
において、配線部をシリ−サイドとすると共に、配線と
拡散層の接触部をもシソサイドとしたことを％徴とする
半導体装置。(1) A semiconductor device in which a diffusion layer is formed in a silicon substrate, in which the wiring portion is made of silicide, and the contact portion between the wiring and the diffusion layer is also made of silicide.
ンチング法によるマスクを用いたシリコンイオン注入法
で形成したシリサイドとすることを特徴とする特許請求
の範囲矛１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the silicide of the wiring portion and the contact portion is silicide formed by a silicon ion implantation method using a mask using a 7-oto-etching method.
スタのゲート’ｆｉｂとして動作することを特徴とする
特許請求の範囲矛２項記載の半導体装置。(3) A semiconductor device according to claim 2, characterized in that a portion of the silicide in the wiring portion operates as a gate fib of a φEMQS type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182183A JPS59136970A (en) | 1983-01-27 | 1983-01-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182183A JPS59136970A (en) | 1983-01-27 | 1983-01-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59136970A true JPS59136970A (en) | 1984-08-06 |
Family
ID=11788441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1182183A Pending JPS59136970A (en) | 1983-01-27 | 1983-01-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59136970A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239623A (en) * | 1985-04-17 | 1986-10-24 | Agency Of Ind Science & Technol | Formation of electrode of semiconductor device |
| JPS6255930A (en) * | 1985-09-05 | 1987-03-11 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH02165628A (en) * | 1988-12-20 | 1990-06-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55125648A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Semiconductor integrated circuit |
| JPS56158454A (en) * | 1980-05-12 | 1981-12-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1983
- 1983-01-27 JP JP1182183A patent/JPS59136970A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55125648A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Semiconductor integrated circuit |
| JPS56158454A (en) * | 1980-05-12 | 1981-12-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239623A (en) * | 1985-04-17 | 1986-10-24 | Agency Of Ind Science & Technol | Formation of electrode of semiconductor device |
| JPS6255930A (en) * | 1985-09-05 | 1987-03-11 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH02165628A (en) * | 1988-12-20 | 1990-06-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2558931B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS58176975A (en) | Method of producing integrated mos field effect transistor circuit | |
| JPS60254766A (en) | Method of producing gage electrode | |
| JP3181695B2 (en) | Method for manufacturing semiconductor device using SOI substrate | |
| JPS6233466A (en) | Manufacture of semiconductor device | |
| KR930003558B1 (en) | Manufacturing method of semiconductor device | |
| JPS6046831B2 (en) | Manufacturing method of semiconductor device | |
| JP4846167B2 (en) | Manufacturing method of semiconductor device | |
| JPS63219152A (en) | Manufacture of mos integrated circuit | |
| JPS59136970A (en) | Semiconductor device | |
| JPS6360549B2 (en) | ||
| JPS6226573B2 (en) | ||
| JPS60193371A (en) | Manufacture of semiconductor device | |
| JPH1098186A (en) | Semiconductor device and its manufacture | |
| JPH047822A (en) | Manufacture of semiconductor device | |
| JPS59112641A (en) | Semiconductor device and manufacture thereof | |
| JPH06163576A (en) | Manufacture of semiconductor device | |
| JPS59115554A (en) | Semiconductor device and manufacture thereof | |
| JPH0431193B2 (en) | ||
| JPS6074478A (en) | Manufacture of semiconductor device | |
| JPH04348531A (en) | Manufacture of field effect transistor | |
| JPH0391245A (en) | Thin-film semiconductor device and manufacture thereof | |
| JPS5988868A (en) | Manufacture of semiconductor device | |
| JPS62281351A (en) | Manufacture of semiconductor device | |
| JPH0658899B2 (en) | Method for manufacturing semiconductor device |