JPS59136952A - Material for semiconductor substrate - Google Patents
Material for semiconductor substrateInfo
- Publication number
- JPS59136952A JPS59136952A JP58010790A JP1079083A JPS59136952A JP S59136952 A JPS59136952 A JP S59136952A JP 58010790 A JP58010790 A JP 58010790A JP 1079083 A JP1079083 A JP 1079083A JP S59136952 A JPS59136952 A JP S59136952A
- Authority
- JP
- Japan
- Prior art keywords
- powder
- alloy
- thermal expansion
- 5mum
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Powder Metallurgy (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
近年、ICの演算速度の向上、トランジスタの電気容量
の増大、Ga−As、FETの出現等により、半導体素
子の駆動時に半導体素子に発生する熱をいかに放熱させ
るかという点が大きな問題となっ通してパッケージ外へ
排出される。従ってこの基板材料には熱伝導度が高い材
料を用いることが好ましい。[Detailed Description of the Invention] In recent years, due to improvements in the operation speed of ICs, increases in the capacitance of transistors, and the appearance of Ga-As and FETs, it has become increasingly important to consider how to dissipate the heat generated in semiconductor devices when they are driven. This is a major problem as the particles are ejected through the package and out of the package. Therefore, it is preferable to use a material with high thermal conductivity for this substrate material.
ところで、近年前記パッケージとして士ラミックを用い
た士ラミックパッケージが多用されている。このパッケ
ージの場合、前記基板が電極取出し用のセラミック枠(
又は板)と一体化されている。従って基板材料としてA
l2O3を主成分とする磁器を使用する場合には、電極
取出し用のセラミック枠(又は板)と一体焼成されるた
め問題ないが熱伝導性を向上させる為WやMo等、電極
取出し用のセラミック枠(又は板)と異種の材料を基板
材料として用いる場合、以下の如き問題が生ずる。Incidentally, in recent years, lamic packages using lamic have been frequently used as the package. In the case of this package, the substrate is a ceramic frame for taking out the electrodes (
or board). Therefore, A as a substrate material.
When using porcelain whose main component is l2O3, there is no problem because it is fired integrally with the ceramic frame (or plate) for taking out the electrodes, but in order to improve thermal conductivity, ceramics such as W or Mo are used for taking out the electrodes. When a material different from the frame (or board) is used as the substrate material, the following problems occur.
即ちWやMo等を基板材料として用いた場合、電極取出
し用のセラミック枠(又は板)との接合は通常銀鑞によ
る鑞付方法が用いられる。この場合WやMo等はセラミ
ックとの熱膨張率の差が大きい為、鑞付工程における加
熱後の冷却時に熱歪によりセラミック枠(又は板)が破
損するという問題が生ずる。That is, when W, Mo, or the like is used as the substrate material, a brazing method using silver solder is usually used to join the ceramic frame (or plate) for taking out the electrode. In this case, since W, Mo, etc. have a large difference in coefficient of thermal expansion from ceramic, a problem arises in that the ceramic frame (or plate) is damaged due to thermal distortion during cooling after heating in the brazing process.
この為、熱膨張率がセラミックと近いFe −Ni合金
又はFe−Ni−C0合金の薄板を基板とセラミック枠
(又は板)の間に介在させることが行なわれているが、
かかる方法は熱伝導上好ましくない。For this reason, a thin plate of Fe-Ni alloy or Fe-Ni-C0 alloy, which has a coefficient of thermal expansion close to that of ceramic, is interposed between the substrate and the ceramic frame (or plate).
Such a method is unfavorable in terms of heat conduction.
一方、熱伝導性が良く、熱膨張率も七ラミツク枠(又は
板)に近いBeOを用いることが考えられているがBe
Oは毒性を有する為、取扱いや製造が困難であり、さら
に人手することも困難で実用的でない。On the other hand, it has been considered to use BeO, which has good thermal conductivity and a coefficient of thermal expansion close to that of a seven-laminate frame (or board);
Since O is toxic, it is difficult to handle and manufacture, and furthermore, it is difficult to handle manually, making it impractical.
本発明は熱伝導率、熱膨張率共に満足し、毒性人手の困
難性等の問題もない半導体基板材料を提供するものであ
り、その要旨は最終製品比5〜2゜wt%のCu粉末と
平均粒度0.5〜5μのW粉末又はtVI□粉末又はW
−Mo合金粉末とを混合成形した後、還元雰囲気中で
焼成したことを特徴とする半導体基板4A料にある。The present invention provides a semiconductor substrate material that satisfies both thermal conductivity and thermal expansion coefficient and is free from problems such as toxicity and difficulty in manual handling. W powder or tVI□ powder or W with an average particle size of 0.5 to 5μ
-Mo alloy powder is mixed and molded, and then fired in a reducing atmosphere.
本発明において、半導体基板材料中のCu比を5〜20
wt%としたのは熱膨張率を6〜8(XIO−”7°C
)の範囲に保たせる為である。即ち、七ラミックの熱膨
張率は6,5〜7.5 (XIO−6/”C)であり、
前述の鑞付工程における破損を防止するには熱膨張率を
6〜8 (x 10−6/”C)の範囲にする必要があ
るからである。In the present invention, the Cu ratio in the semiconductor substrate material is 5 to 20.
The coefficient of thermal expansion was set as wt% from 6 to 8 (XIO-”7°C
) to keep it within the range. That is, the coefficient of thermal expansion of heptaramic is 6.5 to 7.5 (XIO-6/"C),
This is because the coefficient of thermal expansion needs to be in the range of 6 to 8 (x 10-6/''C) in order to prevent damage during the above-mentioned brazing process.
又、半導体素子として近年多用されているGa −As
を用いる場合Ga−Asの熱膨張率が6.7 (XIO
−〇/ ”C)であり、かつSiに比し、非常にもろい
為、素子を塔載する基板の熱膨張率を素子に近づける必
要がある。この点からも熱膨張率を6〜8 (X 10
−0/°C)にする必要があり、その為にはCu比を5
〜20wt%とする必要がある。In addition, Ga-As, which has been widely used as a semiconductor element in recent years,
When using Ga-As, the thermal expansion coefficient is 6.7 (XIO
-〇/ ``C) and is extremely brittle compared to Si, so it is necessary to make the coefficient of thermal expansion of the substrate on which the element is mounted close to that of the element. From this point of view, the coefficient of thermal expansion should be set to 6 to 8 ( X 10
-0/°C), and for that purpose the Cu ratio must be 5
It is necessary to set it to ~20wt%.
次にW粉末、MO粗粉末平均粒度を0.5〜5μとした
のは、05μ以下になった場合Cuとの混合粉末を通常
のプレス成形法にて成形すると粉末のカサが大きくなり
、加圧成形時粉末間に含有する空気のため成形密度を上
げることが困難となる。又かがる微細な粉末は多量の酸
素その他のガスを粉末表面に吸着しており焼成時に吸着
ガスを放出するため焼成後の合金に多くの空孔が残る為
である。Next, the reason why the average particle size of W powder and MO coarse powder is set to 0.5 to 5μ is that when the particle size is less than 0.5μ, the bulk of the powder becomes large when the mixed powder with Cu is molded using the normal press molding method. It is difficult to increase the compaction density due to the air contained between the powders during compaction. This is because the fine powder that sinters adsorbs a large amount of oxygen and other gases on the powder surface and releases the adsorbed gas during firing, leaving many pores in the alloy after firing.
一方平均粒度5μ以上の粗粒W%Mo又はW、 M。On the other hand, coarse particles W%Mo or W, M with an average particle size of 5μ or more.
の合金粉末を用いCuとの緻密な合金を得るためには1
500°C以上の高温にて焼結せねばならない。In order to obtain a dense alloy with Cu using alloy powder of
It must be sintered at a high temperature of 500°C or higher.
しかるにかかる高温においてはCuの蒸発による消失が
激しく組成のバラツキ及変動が生じ所定の組成の合金を
得ることが困難になる。この為平均粒度を5μ以下にす
る必要があるのである。However, at such high temperatures, Cu is rapidly lost by evaporation, resulting in variations and fluctuations in the composition, making it difficult to obtain an alloy with a predetermined composition. For this reason, the average particle size needs to be 5 microns or less.
伺、本発明においてより好ましい材料を得るには、焼成
温度は1200°C〜1500°C焼成時間は0.5〜
2Hで焼成することが好ましい。However, in order to obtain a more preferable material in the present invention, the firing temperature is 1200°C to 1500°C and the firing time is 0.5°C to 1500°C.
It is preferable to bake at 2H.
即ち焼成中にCuが溶解しW粒子の周囲を充すこと及び
W、 Mo及W、Mo合金粒子同志の焼結が進行する必
要があり1200°C以上望ましくは1300’”C以
」二の高温で焼成する必要がある。但し、前述のごと(
1500°Cを越えることは望ましくない。That is, it is necessary for Cu to melt and fill the surroundings of the W particles during firing, and for the sintering of W, Mo, W, and Mo alloy particles to proceed, so the heating temperature is 1200°C or higher, preferably 1300°C or higher. Requires firing at high temperatures. However, as mentioned above (
It is undesirable to exceed 1500°C.
又、0.5〜2Hを逸脱する焼成では安定した合金を得
にくい。Moreover, it is difficult to obtain a stable alloy by firing outside of 0.5 to 2H.
以下実施例について説明する。Examples will be described below.
実施例
0第1表に示す工うな種々の平均粒径を有するWMoあ
るいはW −Mo合金粉末と−325,meshの銅粉
を第1表に示す組成に配合しアトライク混合機で3時間
均一混合した粉末を30×30×5/nILの大きさに
] t 7cm ”の圧力で型押した後火々の焼結条件
(第1表)でH2ガス雰囲気中で焼結を行った。Example 0 WMo or W-Mo alloy powders having various average particle sizes as shown in Table 1 and copper powder of -325 mesh were blended into the composition shown in Table 1 and uniformly mixed for 3 hours using an Attrike mixer. The resulting powder was pressed into a size of 30 x 30 x 5/nIL at a pressure of 7 cm'', and then sintered in an H2 gas atmosphere under the hot sintering conditions (Table 1).
0なお、第1表中の試料番号7.19.26は通常のプ
レス成形法では良好な型押体が得られないため、静水圧
成形法で得だものを焼結した。Note that sample numbers 7, 19, and 26 in Table 1 could not be obtained with a good stamped body by ordinary press molding, so they were sintered by isostatic pressing.
・第1表の試料番号11は試料番号5と同一の型押体を
1180°CX2Hで焼結したものを6t/Qn2の圧
力で再加圧し1180°cxzn’c再焼結する工程を
2回繰返して緻密化を計った比較試料である。・Sample No. 11 in Table 1 is the same stamped body as sample No. 5, sintered at 1180°C This is a comparison sample that was repeatedly densified.
0かくして得られた合金について熱膨張係数および熱伝
導率を測定しその結果を第1表に示す。The thermal expansion coefficient and thermal conductivity of the thus obtained alloy were measured and the results are shown in Table 1.
第 1 表
第1表のうち試料番号3.15.24・の焼結合金Si
チップの塔載基板材料として用いたICパツージはIC
実装工程でのSiチップや他の外囲基であるA7203
との熱膨張係数の差が小さいためらの熱歪を生ぜず、ま
たデバイスとしては熱放性が極めて良好であるため寿命
が伸び信頼性のいすぐれたICを得ることが出来た。Table 1 Sintered alloy Si of sample number 3.15.24 in Table 1
The IC parts used as the substrate material for the chip are IC
A7203 which is a Si chip or other surrounding group in the mounting process
Because the difference in coefficient of thermal expansion is small, no thermal distortion occurs, and the device has extremely good heat dissipation, so it was possible to obtain an IC with a long life and excellent reliability.
以上の如く本発明により得られた半導体基板拐は熱伝導
度、熱膨張係数共にすぐれた材料であ、毒性や入手の困
難性という問題もない。大吉半導体に対応しうる半導体
基板利料である。As described above, the semiconductor substrate obtained by the present invention is a material with excellent thermal conductivity and coefficient of thermal expansion, and there are no problems of toxicity or difficulty in obtaining it. This is a semiconductor substrate fee that can correspond to Daikichi Semiconductor.
Claims (1)
05〜5μのW粉末又はMo粉末又はW −Mo 合金
粉末とを混合成形した後、還元雰囲気中で焼成しkこと
を特徴とする半導体基板材料。(1) Cu powder with a final product ratio of 5 to 2 Uwt% and W powder or Mo powder or W-Mo alloy powder with an average particle size of 05 to 5 μ are mixed and molded, and then fired in a reducing atmosphere. semiconductor substrate materials.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58010790A JPS59136952A (en) | 1983-01-25 | 1983-01-25 | Material for semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58010790A JPS59136952A (en) | 1983-01-25 | 1983-01-25 | Material for semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59136952A true JPS59136952A (en) | 1984-08-06 |
Family
ID=11760131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58010790A Pending JPS59136952A (en) | 1983-01-25 | 1983-01-25 | Material for semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59136952A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0784341A4 (en) * | 1995-06-23 | 1997-05-14 | Toho Kinzoku Kk | Method of manufacture of material for semiconductor substrate, material for semiconductor substrate, and package for semiconductor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5062776A (en) * | 1973-10-05 | 1975-05-28 |
-
1983
- 1983-01-25 JP JP58010790A patent/JPS59136952A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5062776A (en) * | 1973-10-05 | 1975-05-28 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0784341A4 (en) * | 1995-06-23 | 1997-05-14 | Toho Kinzoku Kk | Method of manufacture of material for semiconductor substrate, material for semiconductor substrate, and package for semiconductor |
EP0784341A1 (en) * | 1995-06-23 | 1997-07-16 | Toho Kinzoku Co., Ltd. | Method of manufacture of material for semiconductor substrate, material for semiconductor substrate, and package for semiconductor |
US5905938A (en) * | 1995-06-23 | 1999-05-18 | Toho Kinzoku Co., Ltd. | Method of manufacturing a semiconductor substrate material |
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